ICS9WDV3501B

IDTTM/ICSTM Voltage Monitor/Watchdog Timer Circuit

1468—05/30/08

VOLTAGE MONITOR/WATCHDOG TIMER CIRCUIT

1

DATASHEET

Advance Information

General Description:

The 9WDV3501 contains 5 voltage monitoring (VMON)

comparators and a watchdog timer circuit. The external voltage

monitor inputs have a reset threshold of approximately 1.0V.

Various power supplies can easily be monitored with these

inputs by use of a simple resistor ladder to divide the supply rail

down to 1.0V.

There are two RESET# outputs. RESET0# is typically

connected to a microprocessor, while RESET1# is typically

connected to peripheral components.

If any of the VMON inputs drops outside the desired operating

range, both RESET# outputs will be asserted simultaneously.

They will stay low as long as VMON is below the threshold.

After VMON rises above the threshold, RESET0# will begin its

timeout count down and return high after the count down

expires. The count down period depends on the value on the

RST0_DLY(1:0) pins. The minimum value is 50ms and the

maximum value is 300ms. When RESET0# is de-asserted, the

RESET1# output will continue to be asserted for an additional

count down period.

Functional Block Diagram

Features:

•

5 Precision Voltage Monitors:

•

Watchdog Timer

•

Selectable Watchdog and Reset Timing

•

Two Active Low reset outputs

•

Precision Timebase with external trim resistor

WatchDog

Timer

Reset Timer 0

50 to 300 ms

nominal

Reset Timer 1

50 to 300 ms

nominal

RESET0#

RESET1#

WTB(1:0)

Watchdog

Edge Detector

WDI

1.00V

Bandgap

+

-

+

-

+

-

+

-

+

-

VMON4

VMON0

VMON1

VMON2

VMON3

RST1_DLY(1:0)

RST0_DLY(1:0)

Osc

RP

Master clock

The RESET1# count down period is set by the RST1_DLY(1:0)

inputs. The

additional delay can range from 50ms to 300ms.

This additional reset is designed to hold the peripheral circuits

in reset after the microprocessor has been released from reset.

The VMON circuitry can continue to operate until VDD drops

below 2.3V.

The watchdog timer monitors transitions on the WDI input. This

input is usually driven by a GPIO line from a microprocessor and

is used to detect when the CPU has entered an infinite loop. If a

transition on the WDI input is not detected within the watchdog

time out period, both RESET# outputs will be asserted and will

be as described in the previous paragraph. The watchdog timer

is restarted when RESET1# goes inactive. The watchdog time

out period is selectable using the WTB(1:0) inputs. The

watchdog can be disabled by pulling the WDI_EN pin low.

The 9WDV3501 incorporates a precision RC oscillator that

utilized an external trimming resistor for maximum accuracy.

The recommend value for this resistor is 30K

Ω.

The 9WDV3501 is available in both commercial and industrial

temperature ranges. It is available in a 20-pin QFN or a 20-pin

TSSOP package.