IDTTM/ICSTM

56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor

1125E—02/26/09

Advance Information

ICS9LPRS502

56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

4

SSOP/TSSOP Pin Description (Continued)

PIN #

PIN NAME

TYPE

DESCRIPTION

29

CPU_STOP#/SRCC5

I/O

Stops all CPU Clocks, except those set to be free running clocks /

Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap

on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as

follows:

0= CPU_STOP#

1 = SRC5

In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values

30

PCI_STOP#/SRCT5

I/O

Stops all PCI Clocks, except those set to be free running clocks /

Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap

on pin 6, PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as

follows:

0= PCI_STOP#

1 = SRC5#

In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37.

31

VDDSRC

PWR

VDD pin for SRC Pre-drivers, 3.3V nominal

32

SRCC6

OUT

Complement clock of low power differential SRC clock pair.

33

SRCT6

OUT

True clock of low power differential SRC clock pair.

34

GNDSRC

PWR

Ground for SRC clocks

35

SRCC7/CR#_E

I/O

SRC7 complement or Clock Request control E for SRC6 pair

The power-up default is SRC7#, but this pin may also be used as a Clock Request control of

SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must

first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled

(high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of

SMBus configuration space

Byte 6, bit 7

0 = SRC7# enabled (default)

1= CR#_E controls SRC6.

36

SRCT7/CR#_F

I/O

SRC7 true or Clock Request control 8 for SRC8 pair

The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8

via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be

disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z),

the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus

configuration space

Byte 6, bit 6

0 = SRC7# enabled (default)

1 = CR#_F controls SRC8.

37

VDDSRC_IO

PWR

Power supply for SRC outputs. 1.05 to 3.3V +/-5%.

38

CPUC2_ITP/SRCC8

OUT

Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The

function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup.

The function is as follows:

Pin 7 latched input Value

0 = SRC8#

1 = ITP#

39

CPUT2_ITP/SRCT8

OUT

True clock of low power differential CPU2/True clock of differential SRC pair. The function of this

pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is

as follows:

Pin 7 latched input Value

0 = SRC8

1 = ITP

40

NC

N/A

No Connect

41

VDDCPU_IO

PWR

Supply for CPU outputs. 1.05 to 3.3V +/-5%.

42

CPUC1_F

OUT

Complement clock of low power differenatial CPU clock pair. This clock will be free-running during

iAMT.

43

CPUT1_F

OUT

True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.

44

GNDCPU

PWR

Ground Pin for CPU Outputs

45

CPUC0

OUT

Complement clock of low power differential CPU clock pair.

46

CPUT0

OUT

True clock of low power differential CPU clock pair.

47

VDDCPU

PWR

Power Supply 3.3V nominal.