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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ICS9LPRS501 датащи(PDF) 14 Page - Renesas Technology Corp |
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ICS9LPRS501 датащи(HTML) 14 Page - Renesas Technology Corp |
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14 / 28 page  IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1121G—05/19/11 Advance Information ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR 14 Intentional PCI Clock to Clock Delay 200 ps nominal steps PCI0 PCI1 PCI2 PCI3 PCI4 PCI_F5 1.0ns Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 0 100 ppm 1,2 33.33MHz output no spread 29.99700 30.00300 ns 2 33.33MHz output spread 30.08421 30.23459 ns 2 33.33MHz output no spread 29.49700 30.50300 ns 2 33.33MHz output nominal/spread 29.56617 30.58421 ns 2 Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 1.71 4 V/ns 1 Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 1.78 4 V/ns 1 Pin to Pin Skew tskew VT = 1.5 V 250 ps 2 Intential PCI to PCI delay tskew VT = 1.5 V 100 187 300 ps 2 Duty Cycle dt1 VT = 1.5 V 45 51 55 % 2 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 103 500 ps 2 Clock period Tperiod Absolute min/max period Tabs Electrical Characteristics - USB48MHz PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -100 0 100 ppm 2,4 Clock period Tperiod 48.00MHz output nominal 20.83125 20.83542 ns 2,3 Absolute min/max period Tabs 48.00MHz output nominal 20.48125 21.18542 ns 2 CLK High Time THIGH 8.216563 11.15198 V CLK Low time TLOW 7.816563 10.95198 V Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 1.2 2 V/ns 1 Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 1.3 2 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 50.8% 55 % 2 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 132.2 350 ps 2 Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -100 0 100 ppm 2, 4 Clock period Tperiod 14.318MHz output nominal 69.82033 69.86224 ns 2, 3 Absolute min/max period Tabs 14.318MHz output nominal 69.83400 70.84800 ns 2 CLK High Time THIGH 29.97543 38.46654 V CLK Low time TLOW 29.57543 38.26654 V Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 1.4 4 V/ns 1 Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 1.7 4 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 53.1 55 % 2 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 138 1000 ps 2 |
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