Timing Diagrams

Timing Mode Sensor Mode

Channel Mode

A

CDS

3-channel internally-defined and pixel-rate mux (00)

B

CDS

1-channel internally-defined mux (01)

C

CIS/SHA

3-channel internally-defined and pixel-rate mux (00)

D

CIS/SHA

1-channel internally-defined mux (01)

Mode A

Note: DATA timing from pixel to pixel is decided by the first rising edge of ADCCLK when

CDSCLK2 is from high to low.

Mode B

HT82V16

Rev. 1.10

5

June 7, 2001

R ( n- 4)

D 15~ D 8

R ( n- 4)

D7 ~ D 0

G ( n- 4)

D 15~ D 8

G ( n- 4)

D7 ~ D 0

B ( n- 4)

D 15~ D 8

B ( n- 4)

D7 ~ D 0

R ( n- 3)

D 15~ D 8

R ( n- 3)

D7 ~ D 0

G ( n- 3)

D 15~ D 8

G ( n- 3)

D7 ~ D 0

B ( n- 3)

D1 5 ~ D8

B ( n- 3)

D7 ~ D 0

R ( n- 2)

D 15~ D 8

R ( n- 2)

D7 ~ D 0

R

G

B

R

G

B

R

G

B

CDS C L K 1

CDS C L K 2

A D CCL K

D 15~ D 0

A nal og I npu t

P i x e l n

P ix e l n + 1

CDS CL K 1

D 15~ D 0

A nal og I npu t

P i x e l n

P i x e l n + 1

P i x e l n + 2

CDS CL K 2

D ( n- 10)

D 15~ D 8

D ( n- 10)

D7 ~ D 0

D ( n- 8)

D 15~ D 8

D ( n- 9)

D7 ~ D 0

D ( n- 9)

D 15~ D 8