ADP3196 datasheet(13/20 Pages) AD

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ADP3196

Rev. 0 | Page 13 of 20

CH4 10V

CH2 1V

CH1 1V

CH3 2V

M 2ms

A CH3

600mV

Figure 8. Typical Start-Up Waveforms

Channel 1: CSREF, Channel 2: SS,

Channel 3: DELAY, Channel 4: Phase 1 Switch Node

CH3 5V

CH2 500mV

CH1 500mV

M 2ms

A CH1

980mV

Figure 9. Typical DAC Code Change Waveforms

Channel 1: CSREF, Channel 2: SS,

Channel 3: Phase 1 Switch Node

CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-

OFF PROTECTION

The ADP3196 compares a programmable current limit setpoint

to the voltage from the output of the current sense amplifier.

The level of current limit is set with the resistor from the

ILIMIT pin to ground. During operation, the current from

ILIMIT is equal to 2/3 of IREF, giving 10 µA normally.

This current, through the external resistor, sets the ILIMIT

voltage, which is internally scaled to give a current limit

threshold of 82.6 mV/V. If the difference in voltage between

CSREF and CSCOMP rises above the current limit threshold,

the internal current limit amplifier controls the internal COMP

voltage to maintain the average output current at the limit.

If the limit is reached and TD3 has completed, a latch-off delay

time starts, and the controller shuts down if the fault is not

removed. The current limit delay time shares the DELAY pin

timing capacitor with the start-up sequence timing. However,

during current limit, the DELAY pin current is reduced to IREF/4.

A comparator monitors the DELAY voltage and shuts off the

controller when the voltage reaches 1.7 V. The current limit

latch-off delay time is therefore set by the current of IREF/4

charging the delay capacitor from 0 V to 1.7 V. This delay is

four times longer then the delay time during the start-up

sequence.

The current limit delay time only starts after the TD3 has

completed. If there is a current limit during startup, the

ADP3196 goes through TD1 to TD3, and then starts the

latch-off time. Because the controller continues to cycle the

phases during the latch-off delay time, if the short is removed

before the 1.7 V threshold is reached, the controller returns to

normal operation and the DELAY capacitor is reset to GND.

The latch-off function can be reset by either removing and

reapplying the supply voltage to the ADP3196, or by toggling

the EN pin low for a short time. To disable the short-circuit

latch-off function, an external resistor should be placed in

parallel with CDLY. This prevents the DELAY capacitor from

charging up to the 1.7 V threshold. The addition of this resistor

causes a slight increase in the delay times.

During startup when the output voltage is below 200 mV, a

secondary current limit is active. This is necessary because the

voltage swing of CSCOMP cannot go below ground. This

secondary current limit controls the internal COMP voltage to

the PWM comparators to 1.5 V. This limits the voltage drop

across the low-side MOSFETs through the current balance

circuitry.

An inherent per phase current limit protects individual phases

if one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal mode

COMP voltage. Typical overcurrent latch-off waveforms are

shown in Figure 10.

CH4 10V

CH2 2V

CH1 1V

CH3 2V

M 2ms

A CH1

600mV

Figure 10. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: COMP,

Channel 3: DELAY, Channel 4: Phase 1 Switch Node

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