REV. A

AD5532B

–13–

2. DAC Mode

In this standard mode, a selected DAC register is loaded serially.

This requires a 24-bit write (10 bits to address the relevant

DAC plus an extra 14 bits of DAC data). (See Figure 4.) MSB

is written first. The user must allow 400 ns (min) between

successive writes in DAC mode.

3. Acquire and Readback Mode

data in a particular DAC register. The relevant channel is

16

µs (max). Following the acquisition, after the next falling

edge of

SYNC, the data in the relevant DAC register is

(See Figure 5.) The full acquisition time must elapse before

the DAC register data can be clocked out.

4. Readback Mode

Again, this is a readback mode but no acquisition is performed.

The relevant channel is addressed (10-bit write, MSB first)

and on the next falling edge of SYNC, the data in the relevant

serial format. (See Figure 5.) The user must allow 400 ns (min)

between the last SCLK falling edge in the 10-bit write and

the falling edge of SYNC in the 14-bit readback. The serial

write and read words can be seen in Figure 10.

This feature allows the user to read back the DAC register

code of any of the channels. In DAC mode, this is useful in

verification of write cycles. In ISHA mode, readback is useful

if the system has been calibrated and the user wants to know

what code in the DAC corresponds to a desired voltage on

the code directly to the DAC register without going through

the acquisition sequence.

INTERFACES

SERIAL INTERFACE

The SER/

PAR pin is tied high to enable the serial interface and

to disable the parallel interface. The serial interface is controlled

by four pins as follows:

SYNC, D

Standard 3-wire interface pins. The

SYNC pin is shared

with the

CS function of the parallel interface.

Data out pin for reading back the contents of the DAC

registers. The data is clocked out on the rising edge of SCLK

and is valid on the falling edge of SCLK.

Mode Bits

There are four different modes of operation as described above.

Cal Bit

In DAC mode, this is a test bit. When it is high it is used to load

all zeros or all ones to the 32 DACs simultaneously. In ISHA mode,

In ISHA mode, the acquisition time is then 45

µs (typ) and

accuracy may be reduced. This bit is set low for normal operation.

Offset_Sel Bit

If this is set high, the offset channel is selected and Bits A4–A0

are ignored.

*SPI and QSPI are trademarks of Motorola, Inc.

Test Bit

This must be set low for correct operation of the part.

A4–A0 Bits

Used to address any one of the 32 channels (A4 = MSB of

address, A0 = LSB).

DB13–DB0 Bits

These are used to write a 14-bit word into the addressed DAC

register. Clearly, this is only valid when in DAC mode.

The serial interface is designed to allow easy interfacing to most

microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI™, SPI™,

DSP56000, TMS320, and ADSP-21xx, without the need for any

glue logic. When interfacing to the 8051, the SCLK must be inverted.

The Microprocessor/Microcontroller Interface section explains

how to interface to some popular DSPs and microcontrollers.

Figures 3, 4, and 5 show the timing diagram for a serial read and

write to the AD5532B. The serial interface works with both a con-

tinuous and a noncontinuous serial clock. The first falling edge of

SYNC resets a counter that counts the number of serial clocks

to ensure the correct number of bits are shifted in and out of the

serial shift registers. Any further edges on

SYNC are ignored until

the correct number of bits are shifted in or out. Once the correct

number of bits for the selected mode have been shifted in or out,

the SCLK is ignored. In order for another serial transfer to take

place, the counter must be reset by the falling edge of

SYNC.

In readback, the first rising SCLK edge after the falling edge of

SYNC causes D

state on the falling edge of the fourteenth SCLK. Data on the

falling edge of the

SYNC signal and on subsequent SCLK falling

not shift data in or out until it receives the falling edge of the

SYNC signal.

PARALLEL INTERFACE (ISHA Mode Only)

The SER/

PAR bit must be tied low to enable the parallel interface

and disable the serial interface. The parallel interface is controlled

by nine pins.

CS

Active low package select pin. This pin is shared with the

SYNC function for the serial interface.

WR

Active low write pin. The values on the address pins are

latched on a rising edge of

WR.

A4–A0

Five address pins (A4 = MSB of address, A0 = LSB). These

are used to address the relevant channel (out of a possible 32).

Offset_Sel

Offset select pin. This has the same function as the Offset_Sel

bit in the serial interface. When it is high, the offset channel

is addressed. The address on A4–A0 is ignored in this case.

Cal

neously. The acquisition time is then 45

µs (typ) and accuracy

may be reduced.