PCAL9714HNMP datasheet(22/56 Pages) NXP

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NXP Semiconductors

PCAL9714

Ultra low-voltage translating 14-bit SPI I/O expander with Agile I/O features, interrupt output, and

reset

P0_1

P1_5

Filtered

P0_1 ~ P1_5

(internal)

tDP

aaa-031778

tDP = [PERIOD of EXT CLOCK] * [Debounce counter(5C)] = 1 μs * 10 = 10 μs (if external clock = 1 MHz, debounce count

Figure 8. Switch debounce timing

6.10 Bus transactions

The PCAL9714 is an SPI bus slave device. Data is exchanged between the master and PCAL9714 through

read and write commands using the SPI bus.

6.10.1 SPI interface (addressable SPI)

This SPI interface of the PCAL9714 is called Global Chip Select or Addressable SPI.

This is a slave-only SPI and not fully duplex, that is, it cannot read/write at the same time.

The SPI interface consists of four pins CS SCLK, SDIN and SDOUT. Table 43 shows the pin names and

description for the SPI interface.

SPI pin name

Pin description

Chip Select input (sometimes called SS).

The chip select line selects the slave device by the host processor (bus

master). If multiple slave devices are connected to the same CS signal all the connected slaves

are selected. Slave devices that are not selected do not interfere with the SPI bus activity. This

signal is sometimes called SS or Slave Select. This is an active LOW signal.

SCLK

Serial clock input.

SCLK is the serial clock input to the device. This clock synchronizes shifting and sampling of the

information on the two data lines. It should be in its idle

state (LOW) during the falling and rising edge of CS.

SDIN

Serial data input (sometimes called MOSI).

Serial Data Input. Data is sampled into the shift register on the rising edge of

SCLK. The device ignores all activity on SDIN except when CS is asserted (LOW). This signal is

sometimes called MOSI or Master Out, Slave In.

SDOUT

Serial data output (sometimes called MISO).

Serial Data Output. SDOUT is always high-impedance except when a

valid slave is addressed with R/W set to one and a valid register address is specified. SDOUT is

driven on the falling edge of SCLK. This signal is sometimes called MISO or Master In, Slave Out.

Table 43. SPI pins

This SPI implementation allows multiple slaves to be connected to the same CS with each slave identified

using a unique slave address. PCAL9714 supports only one address pin or 4 slave addresses, as shown in

Section 6.1.

The data transfers are [16 + (N × 8)] bits wide for N bytes of data with MSB transferred first. The first 7 bits

indicate the address of the slave to be accessed, the eighth bit indicates the types of access (read or write), the

next 8 bits specify the register address, and the last N × 8 bits consist of data.

PCAL9714

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 1 May 2023

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