MPL3150A2ST1 datasheet(21/46 Pages) NXP

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NXP Semiconductors

MPL3150A2S

I2C precision pressure sensor

14.8 FIFO setup registers

14.8.1 F_STATUS - FIFO status register (address 0Dh)

Bit

Symbol

F_OVF

F_WMRK_FLAG

F_CNT[5:0]

Reset

Access

Table 21. F_STATUS - FIFO status register (address 0Dh) bit allocation

F_OVF

F_WMRK_FLAG

Event description

—

No FIFO overflow events detected.

—

FIFO overflow event detected.

—

No FIFO watermark events detected.

—

FIFO watermark event detected. FIFO sample count greater than watermark

value

Table 22. F_STATUS - FIFO status register (address 0Dh) bit description

The F_OVF and F_WMRK_FLAG flags remain asserted while the event source is still active, but the

user can clear the FIFO interrupt bit flag in the interrupt source register (INT_SOURCE) by reading the

F_STATUS register. Therefore, the F_OVF bit flag will remain asserted while the FIFO has overflowed and the

F_WMRK_FLAG bit flag will remain asserted while the F_CNT value is greater than then F_WMRK value.

Bit

Symbol

Description

5 to 0

F_CNT

FIFO sample counter. F_CNT[5:0] bits indicate the number of samples currently stored

in the FIFO buffer.

00_0000 — indicates that the FIFO is empty (reset value)

00_0001 to 10_0000 — indicates 1 to 32 samples stored in FIFO

Table 23. F_STATUS - FIFO status register (address 0Dh) bit description

14.8.2 F_DATA - FIFO data register (address 0Eh)

F_DATA is a read only address which provides access to 8-bit FIFO data. FIFO holds a maximum of 32

samples, a maximum of 5 × 32 = 160 data bytes of samples can be read. When F_MODE bit in FIFO SETUP

(F_SETUP) register is set to logic '1', the F_DATA pointer shares the same address location as OUT_P_MSB

(01h), therefore all accesses of the FIFO buffer data use the I2C address 01h. Reads from the other data

registers (02h, 03h, 04h, 05h) will return a value of 00h.

Note: The FIFO will NOT suspend to data accumulation during read transactions to F_DATA.

Bit

Symbol

F_DATA[7:0]

Reset

Access

Table 24. F_DATA - FIFO data register (address 0Eh) bit allocation

MPL3150A2S

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 8 May 2023

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