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VPA2000 датащи(PDF) 21 Page - Renesas Technology Corp |
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VPA2000 датащи(HTML) 21 Page - Renesas Technology Corp |
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21 / 25 page ![]() VPA2000 Product Data March 11, 2010 21 LAYOUT GUIDELINES To optimize the device performance, follow these layout guidelines: 1. Place the inductor and diode as close as possible to Pin19 (SWN). 2. Pin20 (GND1) is the power ground of the boost converter. Return the boost output capacitors’ ground connections to this pin while minimizing the loop area created from pin 19 through the diode D1, through the output capacitors, and back to pin 20. 3. Separate all grounds on the top layer and connect all ground connections through vias to the ground plane. 4. Locate all feedback resistor dividers close to the feedback pins. Keep the traces from feedback pins to the resistor dividers as short as possible. 5. Keep the traces from SWN to CGHFLY to D2 and D3 short. 6. Keep the traces from SWN to CGLFLY to D4 and D5 short. 7. Place output capacitors COUT1, CLDO, and CVCORE close to their respective output pins. 8. Keep all input decoupling capacitors close to the input pins and return their ground connections directly to the appropriate ground pin. 6 5 2 3 4 13 14 17 16 15 18 1 Copper AVDD VIN Vias to ground plane Vias to power plane Vias to ground plane CAVDD1 CAVDD2 D1 L1 Figure 38. Optimized Layout for Boost Converter |
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