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MPC5566MZP132 датащи(PDF) 16 Page - Freescale Semiconductor, Inc |
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MPC5566MZP132 датащи(HTML) 16 Page - Freescale Semiconductor, Inc |
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16 / 54 page ![]() MPC5566 Microcontroller Data Sheet, Rev. 0 Preliminary—Subject to Change Without Notice Electrical Characteristics Freescale Semiconductor 16 38 VRL Differential Voltage VRL – VSSA –100 100 mV 39 Analog Reference High Voltage VRH VDDA – 0.1 VDDA + 0.1 V 40 VREF Differential Voltage VRH – VRL 4.5 5.25 V 41 VSSSYN to VSS Differential Voltage VSSSYN – VSS –50 50 mV 42 VRCVSS to VSS Differential Voltage VRCVSS – VSS –50 50 mV 43 VDDF to VDD Differential Voltage2 VDDF – VDD –100 100 mV 43a VRC33 to VDDSYN Differential Voltage VRC33 – VDDSYN –0.1 0.119 V 44 Analog Input Differential Signal Range (with common mode 2.5V) VIDIFF – 2.5 2.5 V 45 Operating Temperature Range — Ambient (Packaged) TA (TL to TH) – 40.0 125.0 οC 46 Slew rate on power supply pins — — 50 V/ms 1 | VDDA0–VDDA1 | must be < 0.1V 2 VPP can drop to 3.0 volts during read operations. 3 During standby operation. If standby operation is not required, VSTBY can be connected to ground. 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 8-way cache enabled (L1CSR0[CORG] = 0b0) 7 Average current measured on Automotive benchmark. 8 Peak currents may be higher on specialized code. 9 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from SRAM to SRAM. Higher currents could be seen if an “idle” loop that crosses cache lines is run from cache. Code should be written to avoid this condition. 10 4-way cache enabled (L1CSR0[CORG] = 0b1) or (L1CSR0[CORG] = 0b0 with L1CSR0[WAM] = 0b1, L1CSR0[WID] = 0b1111, L1CSR0[WDD] = 0b1111, L1CSR0[AWID] = 0b1, and L1CSR0[AWDD] = 0b1) 11 Preliminary. Final specification pending characterization. 12 Power requirements for the VDD33 supply are dependent on the frequency of operation and load of all I/O pins, and the voltages on the I/O segments. See Table 11 for values to calculate power dissipation for specific operation. 13 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Table 10 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 14 Absolute value of current, measured at V IL and VIH. 15 Absolute value of current, measured at V IL and VIH. 16 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and pad_mh. 17 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae. 18 VSSA refers to both VSSA0 and VSSA1. | VSSA0–VSSA1 | must be < 0.1V 19 Up to 0.6 volts during power up and power down. Table 9. DC Electrical Specifications (continued) Num Characteristic Symbol Min Max Unit |
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