13 of 30

May 12, 2010

IDT Confidential

No Acknowledge Bit (NACK)

The no-acknowledge bit is used to indicate the completion of a block read operation, or an attempt to modify a write-protected register. The bus

master releases Serial Data (SDA) after sending eight bits of data, and during the 9th clock pulse period, and does not pull Serial Data (SDA) Low.

Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven

Low.

Memory Addressing

To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master

sends the Device Select Code, shown in the next table (on Serial Data (SDA), most significant bit first).

Device Select Code

Notes:

1. The most significant bit, b7, is sent first.

2. SA0, SA1, and SA2 are compared against the respective external pins on the TSE2002B3C.

The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Select Address (SA2, SA1, SA0). To address the memory array, the

4-bit Device Type Identifier is 1010b; to access the write-protection settings, it is 0110b; and to access the Temperature Sensor settings is 0011b.

Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (SA0, SA1, SA2)

inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable

(SA0, SA1, SA2) inputs.

The 8th bit is the Read/Write bit (R/W#). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If

the device does not match the SPD Device Select code, the SPD section deselects itself from the bus, and goes into Standby mode. The I2C oper-

ating modes are shown in the following table.

Memory Area

Function

Device Type Identifier

Select Address Signals

R/W#

b71

b6

b5

b4

b3

b2

b1

b0

Read/Write SPD Memory

1

0

1

0

SA2

SA1

SA0

R/W#

Set Write Protection (SWP)

01

1

0

VSSSPD

VSSSPD

VHV

0

Clear Write Protection (CWP)

VSSSPD

VDDSPD

VHV

0

Permanently Set Write Protection (PSWP)2

SA2

SA1

SA0

0

Read SWP

VSSSPD

VSSSPD

VHV

1

Read PSWP2

SA2

SA1

SA0

1

Read/Write Temperature Registers

0

0

1

1

SA2

SA1

SA0

R/W#