SLG46867MTR datasheet(2/209 Pages) RENESAS

2 / 209 page

Datasheet

28-Feb-2023

CFR0011-120-00

Revision 3.21

Page 2 of 208

SLG46867

GreenPAK Programmable Mixed-Signal Matrix

with Dual 44 m

Ω/2 A P-FET

Contents

General Description ................................................................................................................................................................ 1

Key Features............................................................................................................................................................................ 1

Applications............................................................................................................................................................................. 1

1 Block Diagram ...................................................................................................................................................................... 8

2 Pinout .................................................................................................................................................................................... 9

2.1 Pin Configuration - MSTQFN- 20L ......................................................................................................................... 9

3 Characteristics ...................................................................................................................................................................13

3.1 Absolute Maximum Ratings .................................................................................................................................13

3.2 Electrostatic Discharge Ratings ...........................................................................................................................13

3.3 Recommended Operating Conditions .................................................................................................................13

3.4 Electrical Characteristics ......................................................................................................................................14

3.5 Timing Characteristics ..........................................................................................................................................18

3.6 Counter/Delay Specifications ...............................................................................................................................22

3.7 OSC Specifications ..............................................................................................................................................22

3.8 ACMP Specifications ............................................................................................................................................24

3.9 Analog Temperature sensor (ts) specifications ....................................................................................................28

3.10 Power Switch Electrical Characteristics (each P-FET) ......................................................................................30

4 User Programmability ........................................................................................................................................................31

5 IO Pins .................................................................................................................................................................................32

5.1 GPIO Pins ............................................................................................................................................................32

5.2 GPI Pins ...............................................................................................................................................................32

5.3 GPO Pins .............................................................................................................................................................32

5.4 Pull-Up/Down Resistors .......................................................................................................................................32

5.5 Fast Pull-up/down during Power-up .....................................................................................................................32

5.6 GPI Structure .......................................................................................................................................................33

5.7 GPIO with I2C Mode IO Structure ........................................................................................................................34

5.8 Matrix OE IO Structure .........................................................................................................................................35

5.9 GPO Structure ......................................................................................................................................................37

5.10 IO Typical Performance .....................................................................................................................................38

6 Connection Matrix ..............................................................................................................................................................41

6.1 Matrix Input Table ................................................................................................................................................42

6.2 Matrix Output Table ..............................................................................................................................................44

6.3 Connection Matrix Virtual Inputs ..........................................................................................................................47

6.4 Connection Matrix Virtual Outputs .......................................................................................................................47

7 Combination Function Macrocells ....................................................................................................................................48

7.1 2-Bit LUT or D Flip-Flop Macrocells .....................................................................................................................48

7.2 2-bit LUT or Programmable Pattern Generator ....................................................................................................51

7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells .............................................................................................53

7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell ...............................................................................................62

7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell ..............................................................................................64

8 Multi-Function Macrocells .................................................................................................................................................68

8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells ..............................................................................68

8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell ..............................................................................77

8.3 CNT/DLY/FSM Timing Diagrams .........................................................................................................................80

8.4 Wake and Sleep Controller ..................................................................................................................................88

9 Analog Comparators ..........................................................................................................................................................93

9.1 ACMP0H Block Diagram ......................................................................................................................................94

9.2 ACMP1H Block Diagram ......................................................................................................................................95

9.3 ACMP2L Block Diagram .....................................................................................................................................96

9.4 ACMP3L Block Diagram .....................................................................................................................................97

9.5 ACMP Typical Performance .................................................................................................................................98

10 Programmable Delay/Edge Detector ............................................................................................................................ 102

10.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT ................................................................... 102

11 Additional Logic Function. Deglitch Filter ................................................................................................................... 103

12 Voltage Reference (Vref) ................................................................................................................................................104

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