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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP3972 датащи(PDF) 23 Page - National Semiconductor (TI) |
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LP3972 датащи(HTML) 23 Page - National Semiconductor (TI) |
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23 / 59 page  I 2C Compatible Interface (Continued) MULTI-BYTE I 2C COMMAND SEQUENCE To correctly function with the Monahan’s Power Manage- ment I 2C the LP3972’s I2C serial interface shall support Random register Multi-byte command sequencing: During a multi-byte write the Master sends the Start command fol- lowed by the Device address, which is sent only once, followed by the 8 Bit register address, then 8-bits of data. The I 2C slave must then accept the next random register address followed by 8 bits of data and continue this process until the master sends a valid stop condition. A Typical Multi-byte random register transfer is outlined below: Device Address, Register A Address, Ach, Register A Data, Ach Register M Address, Ach, Register M Data, Ach Register X Address, Ach, Register X Data, Ach Register Z Address, Ach, Register Z Data, Ach, Stop Note: the PMIC is not required to see the I 2C device address for each transaction. A, M, X, and Z are Random numbers. 20207642 INCREMENTAL REGISTER I 2C COMMAND SEQUENCE The LP3972 supports address increment (burst mode). When you have defined register address n data bytes can be sent and register address is incremented after each data byte has been sent. Address incrimination may be required for non XScale applications. User can define whether multi- byte (default) to random address or address incrimination will be used. 20207643 www.national.com 23 |
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