ADT7481ARMZ datasheet(19/24 Pages) AD

19 / 24 page

ADT7481

Rev. 0 | Page 19 of 24

Remember that some of the ADT7481 registers have different

addresses for read and write operations. The write address of a

written to that register, but it may not be possible to read data

from that address. The read address of a register must be

written to the address pointer before data can be read from that

ALERT OUTPUT

Pin 8 can be configured as an ALERT output. The ALERT out-

put goes low whenever an out-of-limit measurement is detected,

or if the remote temperature sensor is open circuit. It is an open-

drain output and requires a pull-up. Several ALERT outputs can

be wire-OR’ed together, so that the common line will go low if

one or more of the ALERT outputs goes low.

The ALERT output can be used as an interrupt signal to a

processor, or it may be used as an SMBALERT. Slave devices on

the SMBus cannot normally signal to the bus master that they

want to talk, but the SMBALERT function allows them to do so.

One or more ALERT outputs can be connected to a common

SMBALERT line connected to the master. When the SMBALERT

line is pulled low by one of the devices, the following procedure

occurs as illustrated in Figure 19.

ALERT RESPONSE

ADDRESS

MASTER SENDS

ARA AND READ

COMMAND

DEVICE SENDS

ITS ADDRESS

START

ACK

DEVICE

ADDRESS

ACK

STOP

MASTER

RECEIVES

SMBALERT

Figure 19. Use of SMBALERT

1. SMBALERT is pulled low.

2. Master initiates a read operation and sends the alert response

address (ARA = 0001 100). This is a general call address that

must not be used as a specific device address.

3. The device with a low ALERT output responds to the alert

response address, and the master reads the address from the

responding device. An LSB of 1 is added because the device

address is comprised of seven bits. The address of the device

is now known and it can be interrogated in the usual way.

4. If more than one device has a low ALERT output, the one

with the lowest device address will have priority, in accor-

dance with normal SMBus arbitration.

5. Once the ADT7481 has responded to the alert response

address, it will reset its ALERT output, provided that the

error condition that caused the ALERT no longer exists. If

the SMBALERT line remains low, the master sends the ARA

again, and so on until all devices with low ALERT outputs

respond.

MASKING THE ALERT OUTPUT

The ALERT output can be masked for local, Remote 1, Remote 2

or all three channels. This is done by setting the appropriate

mask bits in either the Configuration 1 register (read address =

0x03, write address = 0x09) or in the consecutive ALERT

To mask ALERTs due to local temperature, set Bit 5 of the

consecutive ALERT register to 1. Default = 0.

To mask ALERTs due to Remote 1 temperature, set Bit 1 of the

Configuration 1 register to 1. Default = 0.

To mask ALERTs due to Remote 2 temperature, set Bit 0 of the

Configuration 1 register to 1. Default = 0.

To mask ALERTs due to any channel, set Bit 7 of the

Configuration 1 register to 1. Default = 0.

LOW POWER STANDBY MODE

The ADT7481 can be put into low power standby mode by

setting Bit 6 (Mon/STBY bit) of the Configuration 1 register

(Read Address 0x03, Write Address 0x09) to 1. The ADT7481

operates normally when Bit 6 is 0. When Bit 6 is 1, the ADC is

inhibited, and any conversion in progress is terminated without

writing the result to the corresponding value register.

The SMBus is still enabled in low power standby mode. Power

consumption in this standby mode is reduced to a typical of

5 μA if there is no SMBus activity, or up to 30 μA if there are

clock and data signals on the bus.

When the device is in standby mode, it is still possible to initiate

a one-shot conversion of both channels by writing to the one-

shot register (Address 0x0F), after which the device will return

to standby. It does not matter what is written to the one-shot

write new values to the limit register while in standby mode.

ALERT and THERM are not available in standby mode and,

therefore, should not be used because the state of these pins is

unreliable.

SENSOR FAULT DETECTION

The ADT7481 has internal sensor fault detection circuitry at its

D+ input. This circuit can detect situations where a remote

diode is not connected, or is incorrectly connected, to the

ADT7481. If the voltage at D+ exceeds VDD − 1 V (typical), it

signifies an open circuit between D+ and D−, and consequently,

trips the simple voltage comparator. The output of this compar-

ator is checked when a conversion is initiated. Bit 2 (D1 open

flag) of the Status Register 1 (Address 0x02) is set if a fault is

detected on the Remote 1 channel. Bit 2 (D2 open flag) of the

Status Register 2 (Address 0x23) is set if a fault is detected on

the Remote 2 channel. If the ALERT pin is enabled, setting this

flag will cause ALERT to assert low.

ADT7481ARMZ датащи(PDF) 19 Page - Analog Devices

ADT7481ARMZ датащи(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL