AD9460 datasheet(19/32 Pages) AD

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AD9460

Rev. 0 | Page 19 of 32

TERMINOLOGY

Analog Bandwidth (Full Power Bandwidth)

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Aperture Delay (tA)

The delay between the 50% point of the rising edge of the clock

and the instant at which the analog input is sampled.

Aperture Uncertainty (Jitter, tJ)

The sample-to-sample variation in aperture delay.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that the

clock pulse should be left in the Logic 1 state to achieve rated

performance. Pulse width low is the minimum time the clock

pulse should be left in the low state. At a given clock rate, these

specifications define an acceptable clock duty cycle.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

no missing codes to 16-bit resolution indicates that all 65,536

codes must be present over all operating ranges.

Integral Nonlinearity (INL)

INL is the deviation of each individual code from a line drawn

from negative full scale through positive full scale. The point

used as negative full scale occurs ½ LSB before the first code

transition. Positive full scale is defined as a level 1½ LSB beyond

the last code transition. The deviation is measured from the

middle of each particular code to the true straight line.

Signal-to-Noise and Distortion (SINAD)

SINAD is the ratio of the rms input signal amplitude to the rms

value of the sum of all other spectral components below the

Nyquist frequency, including harmonics but excluding dc.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms input signal amplitude to the rms

value of the sum of all other spectral components below the

Nyquist frequency, excluding the first six harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the rms signal amplitude to the rms value

of the peak spurious spectral component. The peak spurious

component may be a harmonic. SFDR can be reported in dBc (that

is, degrades as signal level is lowered) or dBFS (always related back

to converter full scale).

Total Harmonic Distortion (THD)

The ratio of the rms input signal amplitude to the rms value of

the sum of the first six harmonic components.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product.

Effective Number of Bits (ENOB)

The effective number of bits for a sine wave input at a given

input frequency can be calculated directly from its measured

SINAD using the following formula:

(

)

6.02

1.76

−

SINAD

ENOB

Gain Error

The first code transition should occur at an analog value of

½ LSB above negative full scale. The last transition should occur

at an analog value of 1½ LSB below the positive full scale. Gain

error is the deviation of the actual difference between first and

last code transitions and the ideal difference between first and

last code transitions.

Maximum Conversion Rate

The clock rate at which parametric testing is performed.

Minimum Conversion Rate

The clock rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed limit.

Offset Error

The major carry transition should occur for an analog value of

½ LSB below VIN+ = VIN−. Offset error is defined as the

deviation of the actual transition from that point.

Out-of-Range Recovery Time

The time it takes for the ADC to reacquire the analog input

after a transition from 10% above positive full scale to 10%

above negative full scale, or from 10% below negative full scale

to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the clock rising edge and the time when all

bits are within valid logic levels.

Power-Supply Rejection Ratio

The change in full scale from the value with the supply

at the minimum limit to the value with the supply at the

maximum limit.

Temperature Drift

The temperature drift for offset error and gain error specifies

the maximum change from the initial (25°C) value to the value

at TMIN or TMAX.

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