Data Sheet
SC-614
© 2003 Sensory Inc.
P/N 80-0210-C
5
DC Electrical Characteristics, TA = 0 to 70°C
PARAMETER
TEST CONDITIONS
MIN TYP
§
MAX UNIT
Positive going threshold
2.4
Negative going threshold
1.8
VDD = 3 V
Hysteresis
0.6
V
Positive going threshold
3.3
Negative going threshold
2.9
RESET_
Threshold changes
VDD = 5.2 V
Hysteresis
0.4
V
VDD = 3 V
2
3
VDD = 4.5 V
3
4.5
VIH
High-level input voltage
VDD = 5.2 V
3.5
5.2
V
VDD = 3 V
0
1
VDD = 4.5 V
0
1.5
VIL
Low-level input voltage
VDD = 5.2 V
0
1.7
V
IOH
¶
High-level output current per pin of I/O port
VOH = 4 V
–2
mA
IOL
¶
Low-level output current per pin of I/O port
VOL = 0.5 V
5
mA
IOH (DAC)
High-level output DAC current
VOH = 4 V
–10
mA
IOL (DAC)
Low-level output DAC current
VDD = 4.5 V
VOL = 0.5 V
20
mA
Ilkg
Input leakage current
Excludes OSCIN
1
µA
I(STANDBY)
Standby current
RESET is low
0.05
10
µA
IDD
†
Operating current
VDD = 4.5 V, FCLOCK = 12.32 MHz
15
mA
I(SLEEP-deep)
VDD = 4.5 V, DAC off, ARM set, OSC disabled
0.05
10
I(SLEEP-mid)
VDD = 4.5 V, DAC off, ARM set, OSC enabled
40
60
I(SLEEP-light)
Supply current
VDD = 4.5 V, DAC off, ARM clear, OSC enabled
60
100
µA
VIO
Input offset voltage
VDD = 4.5 V, Vref = 1 to 4.25 V
25
50
mV
R(PULLUP)
F port pullup resistance
VDD = 5 V
70
150
K
Ω
∆f(RTO-trim) Trim deviation
RRTO = 470 KΩ, VDD = 4.5 V, TA = 25°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)
‡
±1%
±3%
∆f(RTO-volt)
Voltage deviation
RRTO = 470 KΩ, VDD = 3.5 to 5.2 V, TA = 25°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)
‡
±1.5%
∆f(RTO-temp) Temperature deviation
RRTO = 470 KΩ, VDD = 4.5 V, TA = 0 to 70°C,
fRTO = 8.192 MHz (PLL setting = 7 Ch)
‡
±0.03
%/°C
∆f(RTO-res)
Resistance deviation
VDD = 4.5 V, TA = 25°C, R(OSC) = 470 KΩ at ±1%,
fRTO = 8.192 MHz (PLL setting = 7 Ch)
‡
±1%
† Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC
output and other outputs are open circuited.
‡ The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored.
§ Typical voltage and current measurement taken at 25
°C
¶ Cannot exceed 15 mA total per internal VDD pin. Port A, B share 1 internal VDD pin; Port C, D share 1 internal VDD.
External Component Absolute Values
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
R(RTO)
RTO external resistance
TA = 25°C, 1% tolerance
470
K
Ω
C(PLL)
PLL external capacitance
TA = 25°C, 10% tolerance
3300
pF
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