A121 Pulsed Coherent Radar (PCR)

Datasheet v1.0

© 2023 Copyright by Acconeer

2023-03-30

Page 6 of 29

2.1

Functional Block Diagram

A121 One Package Solution

A121 Silicon

TX

RX

PLL

LDOs

PoR

Program

memory

Data

memory

SPI (4)

INTERRUPT

XIN

XOUT

CTRL (optional)

1.8V Single

power supply.

1.8V or 3.3V IO

power supply.

ENABLE

Digital

Power

Timing

mmWave Radio

Tx ant.

Rx ant.

Figure 2.1 The A121 functional block diagram.

The A121 silicon is divided into four functional blocks: Power, Digital, Timing and mmWave radio.

The Power functional block includes LDOs and a Power on Reset (PoR) block. Each LDO creates its

own voltage domain. The PoR block generates a Reset signal on each power-up cycle. To operate the

A121, an external host CPU such as a microcontroller (MCU) is required.

The host application interfaces the Power functional block of the sensor via 1.8 V Single power

supply, 1.8 V or 3.3 V IO power supply and ENABLE.

The Digital functional block includes sensor control and the data memory stores the radar sweep data.

The external host CPU interfaces the A121 via an SPI interface, INTERRUPT signal and optional

CTRL signal. The SPI, INTERRUPT, CTRL and ENABLE interfaces support 1.8 V or 3.3 V IO

voltage levels.

The Timing block includes the timing circuitry. The PLL digital clock output is used to drive internal

digital logic and is generated by a crystal oscillator that requires an external crystal (XIN/XOUT).

Supported frequency of the external crystal is 24 MHz.

The mmWave radio functional block generates and receives radar pulses and includes transmitter

(TX), receiver (RX) and interfaces toward the antennas in package. The A121 operates in the 57-64

GHz band.