ZSSC3136 Datasheet

© 2016 Integrated Device Technology, Inc.

13

January 22, 2016

2.3.4.

Analog-to-Digital Converter

The A/D converter is implemented using full-differential switched-capacitor technique.

Programmable ADC resolutions are rADC=<13, 14>bit.

The A/D conversion is integrating, inherently monotone, and insensitive to short and long term instability of the

clock frequency. The conversion time tADC depends on the desired resolution and can be roughly calculated by

equation (1):













=

2

f

2

t

OSC

r

ADC

ADC

(1)

Where

rADC

Resolution of A/D conversion

fOSC

Frequency of internal oscillator (refer to 1.3.1)

Refer to the ZSSC313x Bandwidth Calculation Sheet for a detailed calculation of sampling time and bandwidth.

The result of the A/D conversion is a relative counter result Z corresponding to the following equation:

)

RS

V

V

(

2

Z

ADC_REF

ADC_DIFF

rADC

−

⋅

=

(2)

Where

rADC

Resolution of A/D conversion

VADC_DIFF

Differential ADC input voltage

VADC_REF

ADC reference voltage (VVBR_T-VVBR_B or VVDDA-VVSSA, if BRREF=1)

RS

Digital ADC Range Shift (RS = 1/16, 1/8, 1/4, 1/2; controlled by the EEPROM contents)

With the RS value, a sensor input signal can be shifted in the optimal input range of the ADC.

The condition required for ensuring the specified accuracy, stability, and non-linearity parameters of the analog

front-end is that the differential ADC input voltage VADC_DIFF does not exceed the range of 10% to 90% of the ADC

reference voltage VADC_REF. This requirement must be met for the whole temperature range and for all sensor

tolerances.