DSP56004ROM datasheet(40/82 Pages) NXP

40 / 82 page

2-16

DSP56004/D, Rev. 3

MOTOROLA

Specifications

External Memory Interface (EMI) DRAM Refresh Timing

EXTERNAL MEMORY INTERFACE (EMI) DRAM REFRESH TIMING

(CL = 50 pF + 2 TTL Loads)

Table 2-9

External Memory Interface (EMI) DRAM Refresh Timing

No.

Characteristics

Sym.

Timing

Mode

Exp.

50 MHz

66 MHz

81 MHz

Unit

Min Max Min Max Min

Max

81 RAS Deassertation to

RAS Assertion

tRP

slow

fast

× T

C – 7

× T

C – 7

113

—

67.1

42.4

—

82 CAS Deassertation to

CAS Assertion

tCPN

slow

fast

× T

C – 7

× T

C – 7

—

54.7

—

83 Refresh Cycle Time

tRC

slow

fast

× T

240

160

—

181.8

121.2

—

148.2

98.8

—

84 RAS Assertion Pulse

Width

tRAS

slow

fast

× T

C – 9

× T

C – 9

111

—

81.9

51.6

—

65.1

40.4

—

85 RAS Deassertation to

RAS Assertion for

Refresh Cycle1

tRP

slow

fast

× T

C – 5

× T

C – 5

—

55.7

—

86 CAS Assertion to RAS

Assertion on Refresh

Cycle

tCSR

TC – 7

—

5.3

—

87 RAS Assertion to CAS

Deassertation on

Refresh Cycle

tCHR

slow

fast

× T

C – 15

× T

C – 15

105

—

75.9

45.6

—

59.1

34.4

—

88 RAS Deassertation to

CAS Assertion on a

Refresh Cycle

tRPC

slow

fast

× T

C – 11

× T

C – 11

—

50.7

—

89 CAS Deassertation to

Data Not Valid

tOFF

0—0

—

Note:

This happens when a Refresh Cycle is followed by an Access Cycle.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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