9.4.1.1 Thermal Considerations

The OPA814 does not require heat sinks or airflow in most applications. The maximum allowed junction

temperature sets the maximum allowed internal power dissipation, as described in the following paragraph.

Do not allow the maximum junction temperature to exceed 150°C.

The operating junction temperature (TJ) is given by TA + PD × RθJA. The total internal power dissipation (PD)

is the sum of quiescent power (PDQ), and additional power dissipated in the output stage (PDL) to deliver load

power. Quiescent power is the specified no-load supply current times the total supply voltage across the part.

PDL depends on the required output signal and load, but for a grounded resistive load, PDL is at a maximum

when the output is fixed at a voltage equal to 1/2 of either supply voltage (for balanced, bipolar supplies). Under

this condition, PDL = VS 2 / (4 × RL), where RL includes feedback network loading.

Be aware that the power in the output stage, and not into the load, determines internal power dissipation.

As a worst-case example, compute the maximum TJ using OPA814 in the circuit of Figure 9-1 operating at the

maximum specified ambient temperature of +85°C and driving a grounded 100-Ω load.

PD = 10 V × 16 mA + 52 / (4 × (100 Ω || 500 Ω)) ≅ 235 mW

Maximum TJ = +85°C + (0.235 W × 122.9°C/W) = 113.9°C.

All actual applications operate at a lower internal power and junction temperature.

9.4.2 Layout Example

Use low-ESR, ceramic bypass

capacitor. Place as close to the

device as possible.

Place output resistors close to

output pin to minimize

parasitic capacitance.

Ground and power planes

removed from inner layers.

Ground fill on outer layers also

removed.

Ground and power planes exist on

inner layers.

Place bypass capacitors

close to power pins.

Remove GND and power planes

under output and inverting pins to

minimize stray PCB capacitance.

CBYP

RF

RG

+

–

VS–

CBYP

VS+

Representative Schematic

1

8

2

7

3

6

4

5

RS

CBYP

CBYP

RS

Remove GND and power planes

under output and inverting pins to

minimize stray PCB capacitance.

Place input resistor close to pin 2 to

minimize parasitic capacitance.

Place feedback resistor on the

bottom of PCB between pins 2 and 6.

RG

Figure 9-7. Layout Recommendation

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OPA814

SBOSA14 – APRIL 2023

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