ISL85014 datasheet(13/22 Pages) RENESAS

13 / 22 page

ISL85014

FN8925 Rev.3.00

Page 13 of 21

Nov 11, 2021

Detailed Description

The ISL85014 combines a synchronous buck controller with a

pair of integrated switching MOSFETs. The buck controller drives

the internal high-side and low-side N-channel MOSFETs to deliver

load currents up to 14A. The buck regulator can operate from an

unregulated DC source, such as a battery, with a voltage ranging

from +3.8V to +18V. An internal 5V LDO voltage regulator is used

to bias the controller. The converter output voltage is

programmed using an external resistor divider and will generate

regulated voltages down to 0.6V. These features make the

regulator suited for a wide range of applications.

The controller uses a current mode loop, which simplifies the

loop compensation and permits fixed frequency operation over a

wide range of input and output voltages. The internal feedback

loop compensation option allows for simple circuit design.

600kHz (FREQ = float) and 300kHz (FREQ = GND) can be

selected as the default switching frequency. The regulator can be

synchronized from 100kHz to 1MHz by SYNC pin as well.

The buck regulator is equipped with a lossless current limit

scheme. The current in the output stage is derived from

temperature compensated measurements of the drain-to-source

voltage of the internal power MOSFETs.

Operation Initialization

The power-on reset circuitry and enable inputs prevent false

start-up of the PWM regulator output. Once all the input criteria

are met (see Figure 31), the controller soft-starts the output

voltage to the programmed level.

Enable and Soft-Start

Chip operation begins after VIN, PVIN, and VDD exceed their rising

POR trip points. If EN is held low externally, nothing happens until

this pin is released. Once the voltage on the EN pin is above 0.6V,

the LDO powers up and soft-start control begins. The ISL85014

operates with Diode Emulation Mode (DEM) during soft-start

regardless of the setting on SYNC pin. The soft-start time is

3ms (typical).

The part is designed to support start-up into a prebiased load

(the prebiased voltage is required to be less than the output

voltage setting). Both high-side and low-side switches are

disabled until the internal SS voltage exceeds the FB voltage

during start-up. It is recommended to connect an RC filter

between an external EN input and the EN pin if a long trace or

pull up to VIN is used. An RC filter of 100kΩ and 1nF is

recommended.

PWM Control Scheme

The ISL85014 employs the current-mode Pulse-Width

Modulation (PWM) control scheme for fast transient response.

The current loop consists of the oscillator, the PWM comparator,

current-sensing circuit, and the slope compensation circuit. The

gain of the current-sensing circuit is typically 55mV/A and the

slope compensation is 780mV/tSS (tSS = period). The control

reference for the current loop comes from the Error Amplifier’s

(EA) output, which compares the feedback signal at FB pin to the

integrated 0.6V reference.

To use internal compensation, connect COMP to ground via a

200Ω resistor. When the default frequency 600kHz is used,

either by floating the FREQ pin or by applying a 600kHz square

wave at the SYNC pin, the voltage loop is internally compensated

with a 30pF and 800kΩ RC network. When the frequency is set

to 300kHz, the voltage loop is internally compensated with a

30pF and 1200kΩ RC network.

The PWM operation is initialized by the clock from the oscillator.

The high-side MOSFET is turned on at the beginning of a PWM

cycle and the current in the MOSFET starts to ramp-up. When the

sum of the current amplifier CSA and the slope compensation

(780mV/tSS) reaches the control reference of the current loop

(COMP), the PWM comparator sends a signal to the PWM logic to

turn off the upper MOSFET and turn on the lower MOSFET. The

lower MOSFET stays on until the end of the PWM cycle. Figure 32

shows the typical operating waveforms during Continuous

Conduction Mode (CCM) operation. The dotted lines illustrate

the sum of the compensation ramp and the current-sense

amplifier’s output.

FIGURE 31. POR CIRCUIT

POR

0.6V

VIN

4.4V

PVIN

3.8V

VDD

3.4V

FIGURE 32. PWM OPERATION WAVEFORMS

VEAMP

VCSA

DUTY

CYCLE

VOUT

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