TL16C752B-EP

3.3-V DUAL UART WITH 64-BYTE FIFO

SGLS153 – FEBRUARY 2003

2

POST OFFICE BOX 655303

description (continued)

The TL16C752B-EP is available in a 48-pin PT (LQFP) package.

14 15

RESET

DTRB

DTRA

RTSA

OPA

RXRDYA

INTA

INTB

A0

A1

A2

NC

36

35

34

33

32

31

30

29

28

27

26

25

16

1

2

3

4

5

6

7

8

9

10

11

12

D5

D6

D7

RXB

RXA

TXRDYB

TXA

TXB

OPB

CSA

CSB

NC

17 18 19 20

47 46 45 44 43

48

42

40 39 38

41

21 22 23 24

37

13

PACKAGE

(TOP VIEW)

NC – No internal connection

AVAILABLE OPTIONS

T

PACKAGE

TA

PACKAGE

– 40

°C to 110°C

TL16C752BTPTREP

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

A0

28

I

Address 0 select bit. Internal registers address selection

A1

27

I

Address 1 select bit. Internal registers address selection

A2

26

I

Address 2 select bit. Internal registers address selection

CDA, CDB

40, 16

I

Carrier detect (active low). These inputs are associated with individual UART channels A and B. A low on these

pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected

in the modem status register (MSR).

CSA, CSB

10, 11

I

Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C752B-EP

for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a low on the respective

CS A and CS B pins.

CTSA,

CTSB

38, 23

I

Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic low on

the CTS pins indicates the modem or data set is ready to accept transmit data from the TL16C752B-EP. Status

can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS

function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation.