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L9961 датащи(PDF) 43 Page - STMicroelectronics

номер детали L9961
подробное описание детали  Battery management system solution
PDF  65 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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L9961 датащи(HTML) 43 Page - STMicroelectronics

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Figure 14. I2C generic WRITE operation
GADG220620221344SA
The elementary WRITE operation consists of:
1.
A START condition
2.
The SLAVE ADDRESS byte (with R/ W = 0) identifying the slave device to be activated
3.
The REGISTER ADDRESS byte identifying the memory address where data has to be written
4.
Two data bytes
5.
An optional CRC byte covering all the previous bytes.
In a block write, the operation can continue by sending other packets formed by two data bytes and an optional
CRC covering the previous two bytes. The REGISTER ADDRESS defined at step 3 will be considered as the
starting address, and the memory address counter will be incremented by 1 at every 2 bytes received.
In case REGISTER ADDRESS saturates, L9961 will generate a NACK and data will not be written into internal
regs.
In case the received CRC is wrong, L9961 generates a NACK and the corresponding data is not written into
internal registers.
The WRITE operation terminates with a STOP condition.
3.10.5
Electrical parameters
All parameters are tested and guaranteed in the following conditions, unless otherwise noted:
VB according to the operating range of Table 2; TJ according to the operating range of Table 5.
Table 31. I2C electrical parameters
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
FSCL
Communication frequency
Guaranteed by
design
80
400
kHz
tLOW
LOW period of the SCL clock
1.3
μs
tHIGH
HIGH period of the SCL clock
0.6
μs
tHD_STA
SCL hold (high) time, after SDA falling edge has created
the START condition, for the START condition to be correctly
detected
0.6
μs
tSU_STA
SCL set-up time to high (SDA already high) before SDA falling
edge creates the START condition sequence (by falling when
SCL is steadily high)
0.6
μs
tHD_DAT
SDA hold time after SCL falling edge
300
-
ns
tSU_DAT
SDA set-up time before SCL rising edge
100
-
ns
tr
Rise time of SDA signal
With 4.7 kΩ pullup
resistor and 40 pF
load
0
300
ns
L9961
I2C protocol layer
DS14012 - Rev 3
page 43/65



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