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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HC05RC16GRS/D датащи(PDF) 92 Page - NXP Semiconductors |
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HC05RC16GRS/D датащи(HTML) 92 Page - NXP Semiconductors |
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92 / 122 page  Instruction Set General Release Specification MC68HC05RC16 — Rev. 3.0 Instruction Set 10.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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