DATASHEET

Low-Cost, 3.3V Zero Delay Buffer

MPC962305

MPC962305 REVISION 8 3/15/16

1

©2016 Integrated Device Technology, Inc.

The MPC962309 is a zero delay buffer designed to distribute high-speed

clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one

reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin

version of the MPC962309 which drives five outputs with one reference input.

The -1H versions of these devices have higher drive than the -1 devices and can

operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which

lock to an input clock presented on the REF pin. The PLL feedback is on-chip and

is obtained from the CLOCKOUT pad.

Features

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1:5 LVCMOS zero-delay buffer (MPC962305)

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1:9 LVCMOS zero-delay buffer (MPC962309)

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Zero input-output propagation delay

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Multiple low-skew outputs

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250 ps max output-output skew

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700 ps max device-device skew

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Supports a clock I/O frequency range of 10 MHz to 133 MHz,

compatible with CPU and PCI bus frequencies

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Low jitter, 200 ps max cycle-cycle, and compatible with Pentium® based

systems

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Test Mode to bypass PLL (MPC962309 only. See Table 3)

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8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin

TSSOP package (MPC962309), all Pb-free

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Single 3.3 V supply

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Ambient temperature range: –40

C to +85C

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Compatible with the CY2305, CY23S05, CY2309, CY23S09

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Spread spectrum compatible

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For drop in replacement for MPC962305 use 2305

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For drop in replacement for MPC962309 use 2309

The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank

B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs

for chip and system testing purposes.

The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During

this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0

A of current draw for the device. The

PLL shuts down in one additional case as shown in Table 3.

Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this

situation, the difference between the output skews of two devices will be less than 700 ps.

All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to

be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.

The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information

page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and

MPC962309-1H, are available to provide faster rise and fall times of the base device.

Pentium II is a trademark of Intel Corporation.

MPC962305

MPC962309

EF SUFFIX

8-LEAD SOIC PACKAGE

Pb-FREE PACKAGE

CASE 751-06

EJ SUFFIX

8-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE

CASE 948J-01

EF SUFFIX

16-LEAD SOIC PACKAGE

Pb-FREE PACKAGE

CASE 751B-05

EJ SUFFIX

16-LEAD TSSOP PACKAGE

Pb-FREE PACKAGE

CASE 948F-01

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016