DATASHEET

3.3 V 1:8 LVCMOS PLL Clock Generator

MPC9653

NRND

MPC9653 REVISION 4 FEBRUARY 4, 2013

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©2013 Integrated Device Technology, Inc.

The MPC9653 is a 3.3 V compatible, 1:8 PLL based clock generator and

zero-delay buffer targeted for high performance low-skew clock distribution in

mid-range to high-performance telecom, networking and computing applications.

With output frequencies up to 125 MHz and output skews less than 150 ps the

device meets the needs of the most demanding clock applications.

Features

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1:8 PLL based low-voltage clock generator

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Supports zero-delay operation

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3.3 V power supply

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Generates clock signals up to 125 MHz

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Maximum output skew of 150 ps

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Differential LVPECL reference clock input

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External PLL feedback

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Drives up to 16 clock lines

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32 lead LQFP packaging

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Ambient temperature range 0°C to +70°C

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Pin and function compatible to the MPC953

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NRND – Not Recommend for New Designs

Use replacement part ICS86953I-147

The MPC9653 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9653 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback).

With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating

frequency range of 25MHz to 62.5MHz or 50MHz to 125MHz. The two available post-PLL dividers selected by VCO_SEL

(divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the

VCO frequency range. The internal VCO of the MPC9653 is running at either 4x or 8x of the reference clock frequency.

The MPC9653 has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as

a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the

selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL

bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not

apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also

causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and

close the phase locked loop, enabling the PLL to recover to normal operation.

The MPC9653 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

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transmission lines. For series terminated transmission lines, each of the MPC9653 outputs can drive one or two traces giving the

devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package.

MPC9653

LOW VOLTAGE

3.3 V LVCMOS 1:8

PLL CLOCK GENERATOR

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A-03

NRND – Not Recommend for New Designs