MPC9448 Rev 7 3/15/16

2

©2016 INTEGRATED DEVICE TECHNOLOGY, INC.

MPC9448 DATASHEET

Figure 1. Logic Diagram

Figure 2. 32-Lead Pinout (Top View)

SYNC

1

0

CCLK

Stop

CLK

CLK_SEL

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q11

Q10

PCLK

CLK_STOP

PCLK

VCC

VCC

VCC

VCC

(All input resistors have a value of 25 k

)

Q3

VCC

Q2

GND

Q1

VCC

Q0

GND

Q8

VCC

Q9

GND

Q10

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

1234

567

8

24

23

22

21

20

19

18

17

16

MPC9448

GND

VCC

Q11

Table 1. Function Table

Control

Default

0

1

CLK_SEL

1

PECL differential input selected

CCLK input selected

OE

1

Outputs disabled (high-impedance state)(1)

1. OE = 0 will high-impedance tristate all outputs independent on CLK_STOP.

Outputs enabled

CLK_STOP

1

Outputs synchronously stopped in logic low state

Outputs active

Table 2. Pin Configurations

Pin

I/O

Type

Function

PCLK, PCLK

Input

LVPECL

Clock signal input

CCLK

Input

LVCMOS

Alternative clock signal input

CLK_SEL

Input

LVCMOS

Clock input select

CLK_STOP

Input

LVCMOS

Clock output enable/disable

OE

Input

LVCMOS

Output enable/disable (high-impedance tristate)

Q0–11

Output

LVCMOS

Clock outputs

GND

Supply

Ground

Negative power supply (GND)

VCC

Supply

VCC

Positive power supply for I/O and core. All VCC pins must be

connected to the positive power supply for correct operation