MK1704A

LOW EMI CLOCK GENERATOR

SSCG

IDT™ LOW EMI CLOCK GENERATOR

2

MK1704A

REV G 051310

Pin Assignment

8 pin (150 mil) SOIC

Output Clock Selection Table

Pin Descriptions

External Components

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50

Ω trace (a commonly

used trace impedance), place a 33

Ω resistor in series with

the clock line, as close to the clock output pin as possible.

The nominal impedance of the clock output is 20

Ω.

Decoupling Capacitor

A decoupling capacitor of 0.01µF must be connected

between VDD and GND on pins 2 and 3.

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

1) The 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible. No vias should be used between decoupling

capacitor and VDD pin. The PCB trace to VDD pin should

be kept as short as possible, as should the PCB trace to the

ground via. Distance of the ferrite bead and bulk decoupling

from the device is less critical.

2) The external crystal should be mounted just next to the

device with short traces. The X1 and X2 traces should not

be routed next to each other with minimum spaces, instead

they should be separated and away from other traces.

3) To minimize EMI the 33

Ω series termination resistor, if

needed, should be placed close to the clock output.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

ICLK

VDD

GND

S0

CLK

S1

LEE

NC

1

2

3

4

8

7

6

5

S1 S0

Input

Min.

Input

Nom.

Input

Max. Mult.

Freq.

spread

vs. CLK

0

0

60

135

140

x1

+0.5, -1.5%

0

1

60

80

120

x1

+0.5, -1.5%

1

0

30

40

60

x1

Down 2.5%

1

1

40

65

100

x1

+0.5, -1.5%

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

ICLK

XI

Connect to a clock input as shown in table above.

2

VDD

Power

Connect to +3.3V or +5V.

3

GND

Power

Connect to ground.

4

CLK

Output

Clock output equal to input frequency.

5

LEE

Input

Low EMI enable. Turns on the spread spectrum when high. Internal pull-up.

6

S1

Input

Frequency select 1 input. Selects input/output clock range per table above.

Internal pull-up.

7

S0

Input

Frequency select 0 input. Selects input/output clock range per table above.

Internal pull-up.

8

NC

-

No connect. Do not connect anything to this pin.