M66596FP datasheet(79/133 Pages) RENESAS

79 / 133 page

M66596FP/WG

rev .1.00

2006.3.14

page 77 of 127

3.4.1.1 Buffer status

Table 3.12 shows the buffer status. The buffer memory status can be confirmed using the BSTS bit and the

INBUFM

bit. The access direction for the buffer memory can be specified using either the DIR bit of the

PIPExCFG

transmitting direction of PIPE1-5.

For a sending direction pipe uses double buffer, software can refer the BSTS bit to monitor the buffer

memory status of CPU side and the INBUFM bit to monitor the buffer memory status of SIE side. In the case like

the BEMP interrupt may not show bufer empty status because the CPU (DMAC) writes data slowly, software

can use the INBUFM bit to tell the end of sending.

Table 3.12 Buffer statuses by BSTS bit and the BSTS bit

ISEL or DIR

BSTS

Buffer memory state

0 (receiving

direction)

There is no received data, or data is being received. Reading from the CPU is

inhibited.

0 (receiving

direction)

There is received data, or a Zero-Length packet has been received. Reading from

the CPU is allowed.

However, because reading is not possible when a Zero-Length packet is received,

the buffer must be cleared.

1 (sending

direction)

The transmission has not been finished. Writing to the CPU is inhibited.

1 (sending

direction)

Writing to the CPU is allowed.

(1) “DBLB=0”(Single buffer) ; The transmission has been finished.

(2) “DBLB=1”(Double buffer) ; The transmission for one side of the buffer has

been finished.

Table 3.13 Buffer statuses by INBUFM bit and the INBUFM bit

ISEL or DIR

INBUF

Buffer memory state

0 (receiving

direction)

Invalid

(sending

direction)

The transmission has been finished. There is no transmitting data.

1 (sending

direction)

There is transmitting data.

3.4.1.2 Buffer clearing

Table 3.14 shows the clearing of the buffer memory by the controller. The buffer memory can be cleared using

the four bits indicated below.

Table 3.14 Buffer clearing

Bit name

BCLR

SCLR

DCLRM

ACLRM

CFIFOCTR register

DxFIFOCTR register

CFIFOSIE register

DxFIFOSEL register

PIPExCTR register

Function

Clears the buffer

memory on the CPU

side

Clears the buffer

memory on the SIE

side

In this mode, after the

data of the specified

pipe has been read,

the buffer memory is

cleared automatically.

See 3.4.3.5

This is the Auto Buffer

Clear mode, in which all

of the received packets

are destroyed.

See 3.4.1.4

Clearing

method

Cleared by writing “1”

“1”: Mode valid

“0”: Mode invalid

“1”: Mode valid

“0”: Mode invalid

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