ICS8546-01 Data Sheet

LOW SKEW, 1-TO 6, CRYSTAL-TO-LVDS FANOUT BUFFER

ICS8546AG-01 REVISION A FEBRUARY 25, 2011

14

©2011 Integrated Device Technology, Inc.

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other

differential signals. Both differential signals must meet the VPP and

VCMR input requirements. Figures 5A to 5E show interface examples

for the CLK/nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. Please consult

with the vendor of the driver component to confirm the driver

termination requirements. For example, in Figure 5A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

Figure 5A. CLK/nCLK Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 5C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 5E.

CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 5B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 5D. CLK/nCLK Input Driven by a

3.3V LVDS Driver

R1

50

Ω

R2

50

Ω

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

R3

125

Ω

R4

125

Ω

R1

84

Ω

R2

84

Ω

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

3.3V

LVPECL

Differential

Input

HCSL

*R3

33

Ω

*R4

33

Ω

CLK

nCLK

3.3V

3.3V

Zo = 50

Ω

Zo = 50

Ω

Differential

Input

R1

50

Ω

R2

50

Ω

*Optional – R3 and R4 can be 0

Ω

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

R1

50

Ω

R2

50

Ω

R2

50

Ω

3.3V

R1

100

Ω

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

Ω

Zo = 50

Ω