ICS844246D Data Sheet

FEMTOCLOCK® CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER w/FANOUT BUFFER

ICS844246DG REVISION A OCTOBER 20, 2011

13

©2011 Integrated Device Technology, Inc.

Schematic Layout

Figure 4 shows an example of ICS844246D schematic. In this

example, the device is operated at VDD = VDDO = 3.3V. An 18pF

parallel resonant 25MHz to 33.33MHz crystal is used. The load

capacitance C1 = 22pF and C2 = 22pF are recommended for

frequency accuracy. Depending on the parasitic of the printed circuit

board layout, these values might require a slight adjustment to

optimize the frequency accuracy. Crystals with other load

capacitance specifications can be used. This will require adjusting

C1 and C2.

As with any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The ICS844246D provides

separate power supplies to isolate noise from coupling into the

internal PLL.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1uf capacitor in each power pin filter should be placed on the device

side of the PCB and the other components can be on the opposite

side of the PCB.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for a wide range of noise frequencies.

This low-pass filter starts to attenuate noise at approximately 10 kHz.

If a specific frequency noise component is known, such as switching

power supplies frequencies, it is recommended that component

values be adjusted and if required, additional filtering be added.

Additionally, good general design practices for power plane voltage

stability suggests adding bulk capacitance in the local area of all

devices.

The schematic example focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure that the logic control inputs are

properly set.

Figure 4. ICS844246D Application Schematic

C2

22pF

Q3

Q2

To Logic

Input

pins

Set Logic

Input to

'1'

VDDO

VDD

VDDO

C8

0.1uF

VDD

Zo_Diff = 100 Ohm

N_SEL1

C10

0.1uF

Zo_Diff = 100 Ohm

nQ5

R3

50

nQ3

RD1

Not Install

C1

22pF

VDD

Q1

Alternate

LVDS

Termination

VDDO

Logic Control Input Examples

3.3V

VDD

3.3V

+

-

R1

100

1 8 p F

Q5

muRat a, B LM18BB221S N1

FB2

1

2

C6

0.1uF

VDDA

C11

10uF

X1

25MHz -33.33MHz

nQ0

Q0

PLL_BY PASS

To Logic

Input

pins

C12

0.1uF

nQ4

RU1

1K

R2

10

R4

50

C4

0. 1u

VDD

+

-

VDD= VDDO=3.3V

C7

0. 1uF

RU2

Not Install

C5

0. 1uF

Q0

nQ1

C9

10uF

Set Logic

Input to

'0'

FB_SEL

LVDS Terminat ion

nQ2

nQ0

C3

10uF

U1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

VDDO

VDDO

nQ2

Q2

nQ1

Q1

nQ0

Q0

PLL_BY PAS S

VDDA

VDD

FB _SE L

XTAL_I N

XTAL_OUT

N_SEL0

GND

GND

N_SEL1

nQ5

Q5

nQ4

Q4

nQ3

Q3

N_SEL0

Q4

RD2

1K

muRata, B LM18BB221SN1

FB1

1

2