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LS80C52 датащи(PDF) 9 Page - Intel Corporation

номер детали LS80C52
подробное описание детали  CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
PDF  23 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

LS80C52 датащи(HTML) 9 Page - Intel Corporation

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8XC525458
DC CHARACTERISTICS (Over Operating Conditions) (Continued)
All parameter values apply to all devices unless otherwise indicated
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
(Note 4)
VOH1
Output High Voltage
VCCb03
V
IOH eb200 mA
(Port 0 in External Bus Mode)
VCCb07
V
IOH eb32 mA
VCCb15
V
IOH eb70 mA
IIL
Logical 0 Input Current
(Ports 1 2 and 3)
b
50
m
AVIN e 045V
ILI
Input leakage Current (Port 0)
g
10
m
AVIN e VIL or VIH
ITL
Logical 1 to 0 Transition Current
(Ports 1 2 and 3)
Commercial
b
650
m
AVIN e 2V
Express
b
750
m
A
RRST
RST Pulldown Resistor
40
225
KX
CIO
Pin Capacitance
10
pF
1 MHz 25 C
ICC
Power Supply Current
(Note 3)
Active Mode
at 12 MHz (Figure 5)
15
30
mA
at 16 MHz
20
38
mA
at 24 MHz
28
56
mA
at 33 MHz (8XC5X-33)
35
56
mA
Idle Mode
at 12 MHz (Figure 5)
5
75
mA
at 16 MHz
6
95
mA
at 24 MHz
7
135
mA
at 33 MHz (8XC5X-33)
7
15
mA
Power Down Mode
5
75
m
A
8XC5X-33
5
50
m
A
NOTES
1 Capacitive loading on Ports 0 and 2 may cause noise pulses above 04V to be superimposed on the VOLs of ALE and
Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed
08V It may be desirable to qualify ALE or other signals with a Schmitt Triggers or CMOS-level input logic
2 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 09 VCC specification when the
address lines are stabilizing
3 See Figures 6 – 9 for test conditions Minimum VCC for Power Down is 2V
4 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature
and 5V
5 Under steady state (non-transient) conditions IOL must be externally limited as follows
Maximum IOL per port pin
10mA
Maximum IOL per 8-bit port
Port 0
26 mA
Ports 1 2 and 3
15 mA
Maximum total IOL for all output pins
71 mA
If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater
than the listed test conditions
9



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