7

ICS94258

Third party brands and names are the property of their respective owners.

Byte 1: CPU, Active/Inactive Register

(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register

(1= enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inverted logic

load of the input frequency select pin conditions.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B3

41

0

M

A

R

D

S

6

t

i

B2

41

1

M

A

R

D

S

5

t

i

B9

31

2

M

A

R

D

S

4

t

i

B8

31

3

M

A

R

D

S

3

t

i

B7

31

4

M

A

R

D

S

2

t

i

B6

31

5

M

A

R

D

S

1

t

i

B3

31

6

M

A

R

D

S

0

t

i

B2

31

7

M

A

R

D

S

Byte 4: Reserved , Active/Inactive Register

(1= enable, 0 = disable)

Byte 5: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

6

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

5

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

4

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

3

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

2

t

i

B-

1

)

e

t

o

N

(

d

e

v

r

e

s

e

R

1

t

i

B-

1

)

e

t

o

N

(

d

e

v

r

e

s

e

R

0

t

i

B-

1

)

e

t

o

N

(

d

e

v

r

e

s

e

R

Byte 6: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

#

0

S

F

6

t

i

B-

X

#

1

S

F

5

t

i

B-

X

#

2

S

F

4

t

i

B1

31

8

M

A

R

D

S

3

t

i

B0

31

9

M

A

R

D

S

2

t

i

B7

21

0

1

M

A

R

D

S

1

t

i

B6

21

1

1

M

A

R

D

S

0

t

i

B5

21

2

1

M

A

R

D

S

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

X

#

3

S

F

6

t

i

B0

11

1

P

G

A

5

t

i

B9

1

0

P

G

A

4

t

i

B2

21

z

H

M

8

4

3

t

i

B2

1

C

I

P

A

O

I

2

t

i

B7

0

X

2

r

o

X

1

-

F

E

R

X

2

=

0

=

t

l

u

a

f

e

d

1

t

i

B6

41

F

_

K

L

C

U

P

C

0

t

i

B7

41

K

L

C

U

P

C

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B8

10

#

E

D

O

M

6

t

i

B0

21

5

K

L

C

I

C

P

5

t

i

B9

11

4

K

L

C

I

C

P

4

t

i

B8

11

3

K

L

C

I

C

P

3

t

i

B5

11

2

K

L

C

I

C

P

2

t

i

B4

11

1

K

L

C

I

C

P

1

t

i

B3

11

0

K

L

C

I

C

P

0

t

i

B2

11

F

_

K

L

C

I

C

P

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B5

11

#

T

E

S

E

R

=

0

,

2

K

L

C

I

C

P

=

1

6

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

5

t

i

B0

31

F

_

I

C

P

L

E

S

/

9

M

A

R

D

S

)

F

_

I

C

P

L

E

S

=

1

=

t

l

u

a

f

e

d

(

4

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

3

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

2

t

i

B-

1

)

d

e

v

r

e

s

e

R

(

1

t

i

B-

0

l

l

i

w

P

O

T

S

_

U

P

C

0

0

=

)

0

:

1

(

t

i

B

s

k

c

o

l

c

U

P

C

p

o

t

s

l

l

i

w

P

O

T

S

_

U

P

C

1

0

=

)

0

:

1

(

t

i

B

s

k

c

o

l

c

P

G

A

,

M

A

R

D

S

,

U

P

C

p

o

t

s

l

l

i

w

P

O

T

S

_

U

P

C

0

1

=

)

0

:

1

(

t

i

B

s

k

c

o

l

c

M

A

R

D

S

,

U

P

C

p

o

t

s

l

l

i

w

P

O

T

S

_

U

P

C

1

1

=

)

0

:

1

(

t

i

B

s

k

c

o

l

c

P

G

A

,

U

P

C

p

o

t

s

0

t

i

B-

0