6.5

Read operations on memory array

Read operations are performed independently of the SWP register value. MSB bit A15 of the address must be

equal to 0.

After the successful completion of a read operation, the device internal address counter is incremented by one, to

point to the next byte address.

Following a start condition the bus master sends a device select code with the RW bit (RW) set to '0'. The

device acknowledges this and waits for the two bytes address. The device responds to each address byte with an

acknowledge bit. Then, the bus master sends another start condition, and repeats the device select code,with the

RW bit set to '1'. The device acknowledges this, and outputs the contents of the data. See in Section 5.5 Device

addressing (Table 5, Table 6 and Table 7) how to address the memory array.

After each byte read (data out), the device waits for an acknowledgement (data in) during the ninth bit time. If

the bus master does not acknowledge during this time, the device terminates the data transfer and switches to its

standby mode after a stop condition.

After the successful completion of a read operation, the device internal address counter is incremented by one, to

point to the next byte address.

Figure 12. Read mode sequences

Dev sel *

Byte addr

Byte addr

Dev sel

Data out 1

Data out N

Current

Address

Read

Dev sel

Data out

Random

Address

Read

Dev sel *

Data out

Sequential

Current

Read

Data out N

Dev sel *

Byte addr

Byte addr

Sequential

Random

Read

Dev sel *

Data out1

ACK

RW

NO ACK

ACK

RW

ACK

ACK

ACK

RW

ACK

ACK

ACK

NO ACK

RW

NO ACK

ACK

ACK

ACK

RW

ACK

ACK

RW

ACK

NO ACK

Note:

The seven most significant bits of the first device select code of a random read must be identical to the seven

most significant bits of the device select code of the write.

M24256X-F

Read operations on memory array

DS12380 - Rev 2

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