LM3743 datasheet(21/23 Pages) NSC

21 / 23 page

Application Information (Continued)

The Output Power (P

OUT) for the Typical Application Circuit

design is (1.8V x 10A) = 18W. The Total Power (P

LOSS), with

an efficiency calculation to complement the design, is shown

below.

The majority of the power losses are due to the low side and

high side MOSFET’s losses. The losses in any MOSFET are

switching (P

SW), conduction losses (PCND), and gate charg-

ing losses (P

GATE)

FET Switching Loss (P

SW)

SW =PSW(ON) +PSW(OFF)

SW =0.5xVIN xIOUT x(tr +tf)xfSW

SW =0.5x5Vx10A x300 kHzx67ns

SW = 503 mW

The Si4866DY has a typical turn-on rise time t

r and turn-off

fall time t

f of 32 ns and 35 ns, respectively. The switching

losses for the upper FET (Q1) is 0.503W. The low side FET

(Q2) does not incur switching losses.

FET Conduction Loss (P

CND)

CND =PCND1 +PCND2

CND1 =I

OUT xRDS(ON) xkxD

CND2 =I

OUT xRDS(ON) x k x (1-D)

DS(ON) = 4.5 m

Ω and the k factor accounts for the increase

in R

DS(ON) due to heating. k = 1.3 at TJ = 100˚C

CND1 = (10A)

2 x 4.5 m

Ω x 1.3 x 0.36

CND2 = (10A)

2 x 4.5 m

Ω x 1.3 x (1 - 0.36)

CND =PCND1 +PCND2

CND = 211 mW + 374 mW = 585 mW

FET Gate Charging Loss (P

GATE)

GATE_H =nx(VCC -VD1 )xQGS xfSW

GATE_L =nxVCC xQGS xfSW

GATES =[1x( 5.0V-0.4V)x22nCx300 kHz]+[1x

(5.0V)x22nCx300 kHz ]

GATES =29mW+33mW=62mW

The value n is the total number of FETs used and Q

GS is the

typical gate-source charge value, which is 21 nC. For the

Si4866DY the gate charging loss is 62 mW.

Thus the total MOSFET losses are:

FET =PSW +PCND +PGATES =

503 mW + 585 mW + 62 mW

FET = 1.15 W

There are few additional losses that are taken into account:

IC Loss (P

IC)

OP =IQ_VCC xVCC

DR =[[(nxQGS xfSW)/D]+[(nxQGS xfSW) / (1–D) ]]

where P

OP is the operating loss, PDR is the driver loss,

Q-VCC is the typical operating VCC current

OP= ( 1.3 mA x 5.0V )

DR=[(1x22nCx300 kHz)/.36]+[(1x22nCx300

kHz)/.64]xV

IC=POP +PDR

IC= 6.5 mW + 137 mW = 143.5 mW

Input Capacitor Loss (P

CAP)

where,

Here n is the number of paralleled capacitors, ESR is the

equivalent series resistance of each, and P

CAP is the dissi-

pation in each. So for example if we use only one input

capacitor of 10m

Ω.

CAP = 230 mW

Output Inductor Loss (P

IND)

IND =I

OUT x DCR

where DCR is the DC resistance. Therefore, for example

IND = (10A)

2 x3m

Ω

IND = 302 mW

Total System Efficiency

LOSS =PFET +PIC +PCAP +PIND

PCB LAYOUT CONSIDERATIONS

To produce an optimal power solution with the LM3743, good

layout and design of the PCB are as important as component

selection. The following are several guidelines to aid in

creating a good layout. For an extensive PCB layout expla-

nation refer to AN-1229.

Separate Power Ground and Signal Ground

Good layout techniques include a dedicated ground plane,

preferably on an internal layer. Signal level components like

the compensation and feedback resistors should be con-

nected to a section of this internal plane, signal ground. The

signal ground section of the plane should be connected to

the power ground at a single point. The best place to connect

the signal ground and power ground is right at the GND pin

of the IC.

Low Impedance Power Path

The power path includes the input capacitors, power FETs,

output inductor, and output capacitors. Keep these compo-

nents on the same side of the PCB and connect them with

thick traces or copper planes on the same layer. Vias add

resistance and inductance to the power path, and have high

impedance connections to internal planes than do top or

bottom layers of a PCB. If heavy switching currents must be

routed through vias and/or internal planes, use multiple vias

in parallel to reduce their resistance and inductance. The

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