AD9380SLASHPCB datasheet(42/60 Pages) AD

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AD9380

Rev. 0 | Page 42 of 60

the HSYNC leading edge. If the VSYNC leading edge occurs in

Quadrant 2 or Quadrant 3, the field is set to 1 and the output

VSYNC leading edge is placed in the center of the line. In this

way, the VSYNC filter creates a predictable relative position

between HSYNC and VSYNC edges at the output.

If the VSYNC occurs near the HSYNC edge, this guarantees

that the VSYNC edge follows the HSYNC edge. This performs

filtering also in that it requires a minimum of 64 lines between

VSYNCs. The VSYNC filter cleans up extraneous pulses that

might occur on the VSYNC. This should be enabled whenever

the HSYNC/VSYNC count is used. Setting this bit to 0 disables

the VSYNC filter. Setting this bit to 1 enables the VSYNC filter.

Power-up default is 0.

0x21—Bit[4] VSYNC Duration Enable

This enables the VSYNC duration block which is designed to

be used with the VSYNC filter. 0 = leave the VSYNC output

duration unchanged. 1 = set the VSYNC output duration based

on Register 0x22. The power-up default is 0.

0x21—Bit[3] Auto-Offset Clamp Mode

This bit specifies if the auto-offset measurement takes place

during clamp or either 10 or 16 clocks afterward. The measure-

ment takes 6 clock cycles. 0 = auto offset measurement takes

place during clamp period. 1 = auto offset measurement is set

by 0x21, Bit 2. Default = 1.

0x21—Bit[2] Auto-Offset Clamp Length

This bit sets the delay following the end of the clamp period

for AO measurement. This bit is valid only if Register 0x21,

Bit 3 = 1. 0 = delay is 10 clock cycles. 1 = delay is 16 clock

cycles. Default = 1.

0x22—Bits[7:0] VSYNC Duration

This is used to set the output duration of the VSYNC, and is

designed to be used with the VSYNC filter. This is valid only if

0x23—Bits[7:0] HSYNC Duration

An 8-bit register that sets the duration of the HSYNC output

pulse. The leading edge of the HSYNC output is triggered by

the internally generated, phase-adjusted PLL feedback clock.

The AD9380 then counts a number of pixel clocks equal to the

value in this register. This triggers the trailing edge of the

HSYNC output, which is also phase-adjusted. The power-up

default is 32.

0x24—Bit[7] HSYNC Output Polarity

This bit sets the polarity of the HSYNC output. Setting this bit

to 0 sets the HSYNC output to active low. Setting this bit to 1

sets the HSYNC output to active high. Power-up default

setting is 1.

0x24—Bit[6] VSYNC Output Polarity

This bit sets the polarity of the VSYNC output (both DVI and

analog). Setting this bit to 0 sets the VSYNC output to active

low. Setting this bit to 1 sets the VSYNC output to active high.

Power-up default is 1.

0x24—Bit[5] Display Enable Output Polarity

This bit sets the polarity of the display enable (DE) for both

DVI and analog. 0 = DE output polarity is negative. 1 = DE

output polarity is positive. The power-up default is 1.

0x24—Bit[4] Field Output Polarity (DVI and Analog)

This bit sets the polarity of the field output signal on Pin 21.

0 = active low = even field; active high = odd field. 1 = active

low = odd field; active high = even field. The power-up default

setting is 1.

0x24—Bit[3] SOG Output Polarity

This bit sets the polarity of the SOGOUT signal (analog only).

0 = active low. 1 = active high. The power-up default setting is 1.

0x24—Bits[2:1] SOG Output Select

These register bits control the output on the SOGOUT pin.

Options are the raw SOG from the slicer (this is the unpro-

cessed SOG signal produced from the sync slicer), the raw

HSYNC, the regenerated sync from the sync filter, which can

generate missing syncs because of coasting or dropout, or the

filtered sync that excludes extraneous syncs not occurring with-

in the sync filter window. The power-up default setting is 11.

Table 16. SOGOUT Polarity Settings

SOGOUT Select

Function

Raw SOG from sync slicer (SOG0 or SOG1)

Raw HSYNC (HSYNC0 or HSYNC1)

Regenerated sync from sync filter

HSYNC to PLL

0x24—Bit[0] Output Clock Invert

This bit allows inversion of the output clock as specified by

clock. The power-up default setting is 0.

0x25—Bits[7:6] Output Clock Select

These bits select the clock output on the DATACK pin. They

include a 1/2× clock, a 2× clock, a 90° phase shifted clock, or

the normal pixel clock. The power-up default setting is 01.

Table 17. Output Clock Select

Select

Result

½× pixel clock

1× pixel clock

2× pixel clock

90° phase 1× pixel clock

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