Preliminary Technical Data

ADM1185

Rev. PrK | Page 7 of 12

Functional Description

The operation of the ADM1185 is explained in this section in

the context of the device in a voltage monitoring and

sequencing application (figure 4, above). In this application, the

ADM1185 will monitor four separate voltage rails, turn on

three regulators in a predefined sequence and generate a power

good signal to turn on a controller when all power supplies are

up and stable.

POWER ON SEQUENCING AND MONITORING

The main supply (in this case 3.3V) powers up the device via

the VCC pin as the voltage rises. A supply voltage of 2.7V to

5.5V is needed to power the device.

The VIN1 pin is monitoring the main 3.3V supply. An external

resistor divider will scale this voltage down for monitoring at

the VIN1 pin. The resistor ratio is chosen so that the VIN1

voltage is 0.6V when the main voltage rises to the preferred

level at start-up (some voltage below the nominal 3.3V level). In

this case, R1 is 4.6K and R2 is 1.2K so that a voltage level of

2.9V will correspond to 0.6V on the non-inverting input of the

first comparator.

TO LOGIC

CORE

ADM1185

3.3V

0V

t

V

0.6V

2.9V supply

gives 0.6V

at VIN1 pin

2.9V

1.2K

4.6K

VIN1

Figure 4.Setting the undervoltage threshold with an external resistor divider

OUT1 is an open drain active high output. In this application,

OUT1 is connected to the enable pin of a regulator. Before the

voltage on VIN1 has reached 0.6V this output is switched to

ground, disabling regulator 1. (Note that all outputs are driven

to ground as long as there is 1V on the VCC pin of the

ADM1185). When the main system voltage reaches 2.9V VIN1

will detect 0.6V and this will cause OUT1 to assert after a

190ms delay. When this occurs the open drain output will

switch high and the external pull-up resistor will pull the

voltage on the regulator 1 enable pin above its turn-on

threshold, turning on the output of regulator 1.

The assertion of OUT1 will turn on Regulator1. The 2.5V

output of this regulator will begin to rise. This will be detected

by input VIN2 (with a similar resistor divider scheme as shows

in figure 5). When VIN2 sees the 2.5V rail rise above its UV

point it will assert output OUT2, turning on Regulator2. A

capacitor can be placed on the VIN2 pin to slow the rise of the

voltage on this pin- this effectively sets a time delay between the

2.5V rail powering up and the next Regulator being enabled.

The same scheme is implemented with the other input and

output pins. Every rail that is turned on via an output pin

OUT(n) is monitored via input pin VIN(n+1).

The final comparator inside the VIN4 pin detects the final

supply turning on, which is 1.2V in this case. All of the output

pins (OUT1-OUT3) are logically ANDed together to generate a

system power good signal (PWRGD). There is an internal

190ms delay associated with the assertion of the PWRGD

output.

Table 4 below is a truth table that steps through the power on

sequence of the outputs. Any associated internal time delays are

also shown.

VOLTAGE MONITORING AFTER POWER ON

Once PWRGD is asserted the logical core latches into a

different mode of operation. During the initial power up phase

each output is directly dependant on an input (i.e. VIN3

asserting causes OUT3 to assert). When power up is complete

this function is redundant.

Once in the PWRGD state the following behavior can be

observed:

•

If the main 3.3V supply that is monitored via VIN1

faults in the power good state then the PWRGD

output is deasserted to warn the downstream

controller and all of the outputs OUT1-OUT3 are

immediately turned off, disabling all locally generated

supplies.

•

If a supply monitored by VIN2-VIN4 fails the

PWRGD output is deasserted to warn the controller

but the other outputs are not deasserted.

Table 5 and table 6 are truth tables that highlight the behavior of

the ADM1185 under various fault situations during normal

operation (i.e. in the mode of operation after PWRGD has

asserted).