3

ICS91730

0794D—05/23/05

Table 1: Frequency Configuration Table

(See I2C Byte 0)

Above is the hard coded 5 bit (32 entry) ROM table.

FS3:0 are ONLY accessible through I2C software programming bits (byte0 bits5:7). FS4 can also be decoded from

FS_IN1 latched input hardware pins.

FS_IN1

→ FS4. Upon power-up the default is to use hardware selection of FS_IN1 latched value.

FS3 = 0, FS2

= 0, FS1 = 0, FS0 = 1 upon power-up (refer to the functionality table on page 1).

To access non-default spread entries in the ROM, byte0 programming should be used. In order to change the power

up default of FS_IN1 = 1 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software

selection by switching this bit to a ‘1’ and then program the desired percentage by changing byte0 bits 7:3.

FS4

FS3

FS2

FS1

FS0

Sprd Type Sprd %

00

00

0

0.60

00

00

1

0.80

00

01

0

1.00

00

01

1

1.25

00

10

0

1.50

00

10

1

2.00

00

11

0

0.50

00

11

1

1.00

01

00

0

0.60

01

00

1

1.00

01

01

0

0.80

01

01

1

CTR SPD

0.3

01

10

0

1.50

01

10

1

1.75

01

11

0

2.00

01

11

1

2.50

10

00

0

3.00

10

00

1

1.25

10

01

0

0.40

10

01

1

0.50

10

10

0

0.70

10

10

1

1.00

10

11

0

1.20

10

11

1

1.50

11

00

0

0.60

11

00

1

0.80

11

01

0

1.00

11

01

1

1.25

11

10

0

1.50

11

10

1

2.00

11

11

0

0.50

11

11

1

1.00

48in/48out

66in/66out

DOWN

SPREAD

(-)

CENTER SPD

(+/-)

14in/27out

DOWN

SPREAD

(-)

CENTER SPD

(+/-)

14in/14out

27in/27out

CENTER SPD

(+/-)

DOWN

SPREAD

(-)

DOWN

SPREAD

(-)