AT43USB351M datasheet(49/101 Pages) ATMEL

49 / 101 page

AT43USB351M

3302E–USB–7/04

Note:

X = A or B

Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are

transferred to a temporary location. They are latched when Timer/Counter1 reaches the value

TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an

unsynchronized OCR1A/OCR1B write. See Figure 14 for an example.

Figure 14. Effects on Unsynchronized OCR1 Latching

Note:

X = A or B

During the time between the write and the latch operation, a read from OCR1A or OCR1B will

read the contents of the temporary location. This means that the most recently written value

always will read out of OCR1A/B

When the OCR1 contains $0000 or TOP, the output OC1A/OC1B is updated to low or high on

the next compare match, according to the settin g s of COM1 A1/COM1A0 or

COM1B1/COM1B0. This is shown in Table 18.

Note: If the compare register contains the TOP value and the prescaler is not in use

(CS12..CS10 = 001), the PWM output will not produce any pulse at all, because up-counting

and down-counting values are reached simultaneously. When the prescaler is in use

Table 17. Compare1 Mode Select in PWM Mode

COM1X1

COM1X0

Effect on OCX1

Not connected

Cleared on compare match, up-counting. Set on compare match,

down-counting (non-inverted PWM).

Cleared on compare match, down-counting. Set on compare match,

up-counting (inverted PWM).

Synchronized

OCR1X Latch

PWM Output OC1X

Counter Value

Compare Value

PWM Output OC1X

Counter Value

Compare Value

Unsynchronized

OCR1X Latch

Glitch

Compare Value Changes

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