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DSP56600FM/AD датащи(PDF) 3 Page - NXP Semiconductors |
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DSP56600FM/AD датащи(HTML) 3 Page - NXP Semiconductors |
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3 / 76 page ![]() DSP56651 Features Preliminary MOTOROLA DSP56651 Technical Data Sheet iii FEATURES RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructions, two cycles for branches and memory accesses • Special branch, byte, and bit manipulation instructions • Support for byte, half-word, and word memory accesses • Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file High Performance DSP56600 Core •1 × engine (e.g., 70 MHz = 70 MIPS) • Fully pipelined 16 × 16-bit parallel multiplier-accumulator (MAC) • Two 40-bit accumulators including extension bits • 40-bit parallel barrel shifter • Highly parallel instruction set with unique DSP addressing modes • Position-independent code support • Nested hardware DO loops • Fast auto-return interrupts • On-chip support for software patching and enhancements • Realtime trace capability via address bus visibility mode Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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