R16DS0137EU0100 Rev.1.0

Page 21

Apr 13, 2021

RAA210040 Datasheet

7.2

Thermal Considerations

Experimental power loss curves, along with

JA from thermal modeling analysis, can evaluate the thermal

consideration for the module. The derating curves are derived from the maximum power allowed while

maintaining the temperature below the maximum junction temperature of +120°C. In applications in which the

system parameters and layout are different from the evaluation board, the customer can adjust the margin of

safety. All derating curves are obtained from tests on a 4-layer thermal test board 4.5x3 inches in size with 2oz

copper on both top and bottom layers and 1oz copper on internal layers. See TB379 for more details. In the actual

application, other heat sources and design margins should be considered.

8.

Package Description

The RAA210040 is integrated into a Dual Flat No-Lead (DFN) package with exposed copper thermal pads. This

package has such advantages as good thermal and electrical conductivity, low weight, and small size. The DFN

package is applicable for surface mounting technology and is becoming more common in the industry. The

embedded laminate substrate and inductor are overmolded with a polymer mold compound to protect these

devices.

The package outline, typical PCB layout pattern, and typical stencil pattern design are shown in the Package

Outline Drawing. TB493 shows the typical reflow profile parameters. These guidelines are general design rules.

You can modify parameters according to your specific application.

8.1

PCB Layout Pattern Design

The bottom of RAA210040 is an embedded laminate substrate, which is attached to the PCB by surface

mounting. The PCB layout pattern is in the Y10.3x3 Package Outline Drawing. The PCB layout pattern is

essentially 1:1 with the DFN package exposed pad and the I/O termination dimensions, except that the PCB lands

are slightly longer than the dual flat no-lead (DFN) embedded laminate package terminations by about 0.3mm.

This extension allows for solder filleting around the package periphery and ensures a more complete and

inspectable solder joint. The thermal lands on the PCB layout should match 1:1 with the package exposed die

pads.

Figure 38. Layout Example - SGND is Connected to PGND at Single Point

Inner Layer

Inner Layer

Inner Layer

RAA210610

SGND Pad

RAA210610

PGND Pad

Slots in PCB

SGND

PGND