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P83C528FBA датащи(PDF) 14 Page - NXP Semiconductors

номер детали P83C528FBA
подробное описание детали  CMOS single-chip 8-bit microcontroller
PDF  26 Pages
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P83C528FBA датащи(HTML) 14 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
80C528/83C528
CMOS single-chip 8-bit microcontrollers
1995 Feb 02
14
AC ELECTRICAL CHARACTERISTICS1, 2
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/tCLCL
1
Oscillator frequency
1.2
16
MHz
tLHLL
1
ALE pulse width
85
2tCLCL–40
ns
tAVLL
1
Address valid to ALE low
8
tCLCL–55
ns
tLLAX
1
Address hold after ALE low
28
tCLCL–35
ns
tLLIV
1
ALE low to valid instruction in
150
4tCLCL–100
ns
tLLPL
1
ALE low to PSEN low
23
tCLCL–40
ns
tPLPH
1
PSEN pulse width
143
3tCLCL–45
ns
tPLIV
1
PSEN low to valid instruction in
83
3tCLCL–105
ns
tPXIX
1
Input instruction hold after PSEN
0
0
ns
tPXIZ
1
Input instruction float after PSEN
38
tCLCL–25
ns
tAVIV
1
Address to valid instruction in
208
5tCLCL–105
ns
tPLAZ
1
PSEN low to address float
10
10
ns
Data Memory
tRLRH
2, 3
RD pulse width
275
6tCLCL–100
ns
tWLWH
2, 3
WR pulse width
275
6tCLCL–100
ns
tRLDV
2, 3
RD low to valid data in
148
5tCLCL–165
ns
tRHDX
2, 3
Data hold after RD
0
0
ns
tRHDZ
2, 3
Data float after RD
55
2tCLCL–70
ns
tLLDV
2, 3
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
2, 3
Address to valid data in
398
9tCLCL–165
ns
tLLWL
2, 3
ALE low to RD or WR low
138
238
3tCLCL–50
3tCLCL+50
ns
tAVWL
2, 3
Address valid to WR low or RD low
120
4tCLCL–130
ns
tQVWX
2, 3
Data valid to WR transition
3
tCLCL–60
ns
tWHQX
2, 3
Data hold after WR
13
tCLCL–50
ns
tRLAZ
2, 3
RD low to address float
0
0
ns
tWHLH
2, 3
RD or WR high to ALE high
23
103
tCLCL–40
tCLCL+40
ns
External Clock
tCHCX
6
High time
20
20
ns
tCLCX
6
Low time
20
20
ns
tCLCH
6
Rise time
20
20
ns
tCHCL
6
Fall time
20
20
ns
Shift Register
tXLXL
4
Serial port clock cycle time
750
12tCLCL
ns
tQVXH
4
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
4
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
4
Input data hold after clock rising edge
0
0
ns
tXHDV
4
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.



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