1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL

PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

87993I DATA SHEET

2

REVISION C 2/18/15

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1

nMR

Input

Pullup

Active LOW Master Reset. When logic LOW, the internal dividers are

reset causing the true outputs Qx to go low and the inverted outputs nQx

to go high. When logic HIGH, the internal dividers and the outputs are

enabled. LVCMOS / LVTTL interface levels.

2

nALARM_RESET

Input

Pullup

When LOW, resets the input bad flags and aligns CLK_SELECTED with

SEL_CLK. LVCMOS / LVTTL interface levels.

3

CLK0

Input

Pulldown Non-inverting differential clock input.

4

nCLK0

Input

Pullup

Inverting differential clock input.

5

SEL_CLK

Input

Pulldown

Clock select input. When LOW, selects CLK0, nCLK0 inputs. When

HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels.

6

CLK1

Input

Pulldown Non-inverting differential clock input.

7

nCLK1

Input

Pullup

Inverting differential clock input.

8, 9, 12

V

EE

Power

Negative supply pins.

10

EXT_FB

Input

Pulldown Differential external feedback.

11

nEXT_FB

Input

Pullup

Differential external feedback.

13

CLK_SELECTED

Output

LOW, when CLK0, nCLK0 is selected, HIGH, when CLK1, nCLK1

is selected. LVCMOS / LVTTL interface levels.

14

INP1BAD

Output

Indicates detection of a bad input reference clock 1 with respect to the

feedback signal. The output is active HIGH and will remain HIGH until the

alarm reset is asserted.

15

INP0BAD

Output

Indicates detection of a bad input reference clock 0 with respect to the

feedback signal. The output is active HIGH and will remain HIGH until the

alarm reset is asserted.

16, 17, 24,

29

V

CC

Power

Core supply pins.

18, 19

nQB2, QB2

Output

Differential output pair. LVPECL interface levels.

20, 21

nQB1, QB1

Output

Differential output pair. LVPECL interface levels.

22, 23

nQB0, QB0

Output

Differential output pair. LVPECL interface levels.

25, 26

nQA1, QA1

Output

Differential output pair. LVPECL interface levels.

27, 28

nQA0, QA0

Output

Differential output pair. LVPECL interface levels.

30

V

CCA

Power

Analog supply pin.

31

MAN_OVERRIDE

Input

Pulldown

Manual override. When HIGH, disables internal clock switch circuitry.

LVCMOS / LVTTL interface levels.

32

PLL_SEL

Input

Pullup

Selects between the PLL and reference clock as the input to the dividers.

When LOW, selects reference clock.When HIGH, selects PLL.

LVCMOS / LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

K

Ω

R

PULLDOWN

Input Pulldown Resistor

51

K

Ω