January 22, 2020

2

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

87016I DATASHEET

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Number

Name

Type

Description

1, 48

VDD

Power

Positive supply pins.

2

CLK0

Input

Pulldown

Single-ended clock input. LVCMOS/LVTTL interface levels.

3

DIV_SELA

Input

Pullup

Controls frequency division for Bank A outputs. See Table 3.

LVCMOS / LVTTL interface levels.

4

DIV_SELB

Input

Pullup

Controls frequency division for Bank B outputs. See Table 3.

LVCMOS / LVTTL interface levels.

5

DIV_SELC

Input

Pullup

Controls frequency division for Bank C outputs. See Table 3.

LVCMOS / LVTTL interface levels.

6

DIV_SELD

Input

Pullup

Controls frequency division for Bank D outputs. See Table 3.

LVCMOS / LVTTL interface levels.

7

CLK_ENA

Input

Pullup

Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive

low. LVCMOS/LVTTL interface levels. See Table 3.

8

CLK_ENB

Input

Pullup

Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive

low. LVCMOS/LVTTL interface levels. See Table 3.

9

CLK_ENC

Input

Pullup

Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive

low. LVCMOS/LVTTL interface levels. See Table 3.

10

CLK_END

Input

Pullup

Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive

low. LVCMOS/LVTTL interface levels. See Table 3.

11

MR/OE

Input

Pullup

Master reset. When LOW, resets the ÷1/÷2 flip flops and sets the outputs to

high impedance. LVCMOS / LVTTL interface levels.

12, 16, 20,

24, 28, 32,

36, 40, 44

GND

Power

Power supply ground

13, 15, 17, 19

QD3, QD2,

QD1, QD0

Output

Bank D single-ended clock outputs. LVCMOS/LVTTL interface levels.

14, 18

VDDOD

Power

Bank D output supply pins.

21, 23, 25, 27

QC3, QC2,

QC1, QC0

Output

Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels.

22, 26

VDDOC

Power

Bank C output supply pins.

29, 31, 33, 35

QB3, QB2,

QB1, QB0

Output

Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels.

30, 34

VDDOB

Power

Bank B output supply pins.

37, 39, 41, 43

QA3, QA2,

QA1, QA0

Output

Bank A single-ended clock outputs. LVCMOS/LVTTL interface levels.

38, 42

VDDOA

Power

Bank B output supply pins.

45

CLK_SEL

Input

Pulldown

Clock select input. When HIGH, selects CLK1, CLK1 inputs.

When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.

46

CLK1

Input

Pullup

Inverting differential clock input.

47

CLK1

Input

Pulldown

Non-inverting differential clock input.