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74LVC2G74DC датащи(PDF) 13 Page - NXP Semiconductors |
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74LVC2G74DC датащи(HTML) 13 Page - NXP Semiconductors |
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13 / 20 page ![]() 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 13 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Measurement points are given in Table 11. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP removal time Test data is given in Table 12. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 8. Load circuitry for switching times mnb142 trec tPHL tPHL tW tPLH tPLH VM VM VM tW VM VM VI GND VI GND SD input VI GND RD input CP input VOH VOL Q output VOH VOL Q output VEXT VCC VI VO mna616 DUT CL RT RL RL PULSE GENERATOR |
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