Voltage Variable RF Attenuator

1MHz to 3000MHz

© 2018 Renesas Electronics Corporation

18

May 7, 2021

F2255

Datasheet

APPLICATIONS INFORMATION

Default Start-up

VMODE must be tied to either GND or Logic High. If the VCTRL pin is left floating, the part will power up in the

minimum attenuation state when VMODE = GND, or the maximum attenuation state when VMODE = High.

VCTRL

The voltage level on the VCTRL pin is used to control the attenuation of the F2255. At VCTRL =0V, the

attenuation is a minimum (maximum) in the negative (positive) slope mode. An increasing (decreasing)

voltage on VCTRL produces an increasing (decreasing) attenuation respectively. The VCTRL pin has an on-chip

pull-up ESD diode so VDD should be applied before VCTRL is applied (see Recommended Operating Conditions

for details). If this sequencing is not possible, then resistor R2 in the application circuit should be set to 1kΩ

to limit the current into the VCTRL pin.

VMODE

The VMODE pin is used to set the slope of the attenuation. The attenuation is varied by VCTRL as described in

the next section. Setting VMODE to a logic LOW (HIGH) will set the attenuation slope to negative (positive). A

negative (positive) slope is defined as an increased (decreased) attenuation with increasing VCTRL voltage. The

Evaluation Kit provides an on-board jumper to manually set the VMODE. Install a jumper on header J2 from

VMODE to the pin marked Lo (Hi) to set the device for a negative (positive) slope (see application circuit).

RF1 and RF2 Ports

The F2255 is a bi-directional device, allowing RF1 or RF2 to be used as the RF input. RF1 has some enhanced

linearity performance, and therefore should be used as the RF input, when possible, for best results. The

F2255 has been designed to accept high RF input power levels; therefore, VDD must be applied prior to the

application of RF power to ensure reliability. DC blocking capacitors are required on the RF pins and should

be set to a value that results in a low reactance over the frequency range of interest.

Power Supplies

The supply pin should be bypassed with external capacitors to minimize noise and fast transients. Supply

noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail. Supply

voltage change or transients should have a slew rate smaller than 1V/20uS. In addition, all control pins

should remain at 0V (+/-0.3V) while the supply voltage ramps or while it returns to zero.