Phlips Semiconductors

Product specification

80C652/83C652

CMOS single-chip 8-bit microcontrollers

1996 Aug 15

7

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP

PLCC

QFP

TYPE

NAME AND FUNCTION

20

22

6, 16,

28, 39

I

connected.

40

44

38

I

Power Supply: This is the power supply voltage for normal, idle, and power-down

operation.

P0.0–0.7

39–32

43–36

37–30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

them float and can be used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external program and data memory. In

this application, it uses strong internal pull-ups when emitting 1s.

P1.0–P1.7

1–8

2–9

40–44,

1–3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7

which are open drain. Port 1 pins that have 1s written to them are pulled high by the

internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled

low will source current because of the internal pull-ups. (See DC Electrical Characteristics:

P1.6

7

8

2

I/O

P1.7

8

9

3

I/O

P2.0–P2.7

21–28

24–31

18–25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, port 2 pins that are externally being pulled low will source current because of the

address byte during fetches from external program memory and during accesses to

external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it

uses strong internal pull-ups when emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function

register.

P3.0–P3.7

10–17

11,

13–19

5,

7–13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As

inputs, port 3 pins that are externally being pulled low will source current because of the

the 80C51 family, as listed below:

10

11

5

I

RxD (P3.0): Serial input port

11

13

7

O

TxD (P3.1): Serial output port

12

14

8

I

INT0 (P3.2): External interrupt

13

15

9

I

INT1 (P3.3): External interrupt

14

16

10

I

T0 (P3.4): Timer 0 external input

15

17

11

I

T1 (P3.5): Timer 1 external input

16

18

12

O

WR (P3.6): External data memory write strobe

17

19

13

O

RD (P3.7): External data memory read strobe

RST

9

10

4

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

ALE

30

33

27

I/O

Address Latch Enable: Output pulse for latching the low byte of the address during an

access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6

the oscillator frequency. Note that one ALE pulse is skipped during each access to external

data memory.

PSEN

29

32

26

O

Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It

is activated twice each machine cycle during fetches from the external program memory.

When executing out of external program memory two activations of PSEN are skipped

during each access to external data memory. PSEN is not activated (remains HIGH) during

no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can

drive CMOS inputs without external pull–ups.

EA

31

35

29

I

External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out

of the internal program memory ROM provided the Program Counter is less than 8192. If

during a RESET, EA is held a TTL LOW level, the CPU executes out of external program

memory. EA is not allowed to float.

XTAL1

19

21

15

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

XTAL2

18

20

14

O

Crystal 2: Output from the inverting oscillator amplifier.

NOTE: