CD4073BMS, CD4081BMS, CD4082BMS

FN3324 Rev 1.00

Page 8 of 11

October 2015

FIGURE 4. LOGIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)

FIGURE 5. SCHEMATIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)

FIGURE 6. LOGIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)

J

3 (4, 10, 11)

2 (5, 9, 12)

1 (6, 8, 13)

A

B

n

p

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

*

3 (11)

p

VDD

n

p

*

2 (12)

n

p

n

n

p

n

p

p

VDD

VSS

n

p

*

4 (10)

p

VSS

n

p

*

5 (9)

n

p

n

VSS

n

VDD

VSS

J

1 (13)

3 (11)

2 (12)

D

C

5 (9)

4 (10)

B

A