83C552 datasheet(2/23 Pages) PHILIPS

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Philips Semiconductors

Product data

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

2002 Sep 03

853-1467 28849

DESCRIPTION

The 80C552/83C552 (hereafter generically referred to as 8XC552)

Single-Chip 8-Bit Microcontroller is manufactured in an advanced

CMOS process and is a derivative of the 80C51 microcontroller

family. The 8XC552 has the same instruction set as the 80C51.

Three versions of the derivative exist:

• 83C552—8 kbytes mask programmable ROM

• 80C552—ROMless version of the 83C552

• 87C552—8 kbytes EPROM (described in a separate chapter)

The 8XC552 contains a non-volatile 8k

× 8 read-only program

memory (83C552), a volatile 256

× 8 read/write data memory, five

8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters

(identical to the timers of the 80C51), an additional 16-bit timer

coupled to capture and compare latches, a 15-source,

two-priority-level, nested interrupt structure, an 8-input ADC, a dual

DAC pulse width modulated interface, two serial interfaces (UART

and I2C-bus), a “watchdog” timer and on-chip oscillator and timing

circuits. For systems that require extra capability, the 8XC552 can

be expanded using standard TTL compatible memories and logic.

In addition, the 8XC552 has two software selectable modes of

power reduction—idle mode and power-down mode. The idle mode

freezes the CPU while allowing the RAM, timers, serial ports, and

interrupt system to continue functioning. The power-down mode

saves the RAM contents but freezes the oscillator, causing all other

chip functions to be inoperative.

The device also functions as an arithmetic processor having

facilities for both binary and BCD arithmetic plus bit-handling

capabilities. The instruction set consists of over 100 instructions: 49

one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz)

crystal, 58% of the instructions are executed in 0.75

µs (0.5 µs) and

40% in 1.5

µs (1 µs). Multiply and divide instructions require 3 µs

µs).

FEATURES

• 80C51 central processing unit

• 8k × 8 ROM expandable externally to 64 kbytes

• ROM code protection

• An additional 16-bit timer/counter coupled to four capture registers

and three compare registers

• Two standard 16-bit timer/counters

• 256 × 8 RAM, expandable externally to 64 kbytes

• Capable of producing eight synchronized, timed outputs

• A 10-bit ADC with eight multiplexed analog inputs

• Two 8-bit resolution, pulse width modulation outputs

• Five 8-bit I/O ports plus one 8-bit input port shared with analog

inputs

• I2C-bus serial I/O port with byte oriented master and slave

functions

• Full-duplex UART compatible with the standard 80C51

• On-chip watchdog timer

• Three speed ranges:

– 3.5 to 16 MHz

– 3.5 to 24 MHz (ROM, ROMless only)

• Three operating ambient temperature ranges:

– P83C552xBx: 0

°C to +70 °C

– P83C552xFx: –40

°C to +85 °C

(XTAL frequency max. 24 MHz)

– P83C552xHx: –40

°C to +125 °C

(XTAL frequency max. 16 MHz)

LOGIC SYMBOL

SU01691

ADC0-7

CMT0

CMT1

CMSR0-5

RST

XTAL1

XTAL2

ALE

PSEN

AVref+

AVref–

STADC

PWM0

PWM1

LOW ORDER

ADDRESS AND

DATA BUS

CT0I

CT1I

CT2I

CT3I

RT2

SCL

SDA

RxD/DATA

TxD/CLOCK

INT0

INT1

VSS

VDD

AVSS

AVDD

HIGH ORDER

ADDRESS AND

DATA BUS

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