CD4071BMS, CD4072BMS, CD4075BMS

FN3323 Rev 0.00

Page 8 of 11

December 1992

FIGURE 4. LOGIC DIAGRAM FOR CD4072BMS (1 OF 2 IDENTICAL GATES)

FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)

FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS (1 OF 3 IDENTICAL GATES)

J

1 (13)

3 (11)

2 (12)

A

B

4 (10)

5 (9)

D

C

n

p

*

8 (5, 13)

p

p

*

2 (4, 12)

*

1 (3, 11)

n

p

n

p

n

p

ALL INPUTS PROTECTED BY

*

CMOS PROTECTION NETWORK

VDD

VSS

n

p

n

9 (6, 10)

n

p

VDD

14

VSS

7

n

n

J

9 (6, 10)

2 (4, 12)

1 (3, 11)

A

B

8 (5, 13)

C